Lines Matching refs:dispc
129 } dispc; variable
250 __raw_writel(val, dispc.base + idx); in dispc_write_reg()
255 return __raw_readl(dispc.base + idx); in dispc_read_reg()
271 spin_lock_irqsave(&dispc.control_lock, flags); in mgr_fld_write()
276 spin_unlock_irqrestore(&dispc.control_lock, flags); in mgr_fld_write()
280 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
282 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
386 dispc.ctx_valid = true; in dispc_save_context()
397 if (!dispc.ctx_valid) in dispc_restore_context()
519 r = pm_runtime_get_sync(&dispc.pdev->dev); in dispc_runtime_get()
531 r = pm_runtime_put_sync(&dispc.pdev->dev); in dispc_runtime_put()
544 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
1129 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1130 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); in dispc_mgr_set_size()
1147 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { in dispc_init_fifos()
1150 dispc.fifo_size[fifo] = size; in dispc_init_fifos()
1156 dispc.fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1166 if (dispc.feat->gfx_fifo_workaround) { in dispc_init_fifos()
1178 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1179 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1202 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1203 if (dispc.fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1204 size += dispc.fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1243 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && in dispc_ovl_set_fifo_threshold()
2254 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2305 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2388 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2445 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, in dispc_ovl_calc_scaling()
2948 return width <= dispc.feat->mgr_width_max && in _dispc_mgr_size_ok()
2949 height <= dispc.feat->mgr_height_max; in _dispc_mgr_size_ok()
2955 if (hsw < 1 || hsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
2956 hfp < 1 || hfp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
2957 hbp < 1 || hbp > dispc.feat->hp_max || in _dispc_lcd_timings_ok()
2958 vsw < 1 || vsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
2959 vfp < 0 || vfp > dispc.feat->vp_max || in _dispc_lcd_timings_ok()
2960 vbp < 0 || vbp > dispc.feat->vp_max) in _dispc_lcd_timings_ok()
2969 return pclk <= dispc.feat->max_lcd_pclk ? true : false; in _dispc_mgr_pclk_ok()
2971 return pclk <= dispc.feat->max_tv_pclk ? true : false; in _dispc_mgr_pclk_ok()
3009 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3010 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3011 FLD_VAL(hbp-1, dispc.feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3012 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3013 FLD_VAL(vfp, dispc.feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3014 FLD_VAL(vbp, dispc.feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3086 if (dispc.syscon_pol) { in _dispc_mgr_set_lcd_timings()
3101 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3160 dispc.core_clk_rate = dispc_fclk_rate() / lck_div; in dispc_mgr_set_lcd_divisor()
3260 return dispc.tv_pclk_rate; in dispc_mgr_pclk_rate()
3266 dispc.tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3271 return dispc.core_clk_rate; in dispc_core_clk_rate()
3535 bool dispc_div_calc(unsigned long dispc, in dispc_div_calc() argument
3561 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); in dispc_div_calc()
3562 lckd_stop = min(dispc / pck_min, 255ul); in dispc_div_calc()
3565 lck = dispc / lckd; in dispc_div_calc()
3671 dispc.core_clk_rate = dispc_fclk_rate(); in _omap_dispc_initial_config()
3688 if (dispc.feat->mstandby_workaround) in _omap_dispc_initial_config()
3838 dispc.feat = dst; in dispc_init_features()
3845 if (!dispc.is_enabled) in dispc_irq_handler()
3848 return dispc.user_handler(irq, dispc.user_data); in dispc_irq_handler()
3855 if (dispc.user_handler != NULL) in dispc_request_irq()
3858 dispc.user_handler = handler; in dispc_request_irq()
3859 dispc.user_data = dev_id; in dispc_request_irq()
3864 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, in dispc_request_irq()
3865 IRQF_SHARED, "OMAP DISPC", &dispc); in dispc_request_irq()
3867 dispc.user_handler = NULL; in dispc_request_irq()
3868 dispc.user_data = NULL; in dispc_request_irq()
3877 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); in dispc_free_irq()
3879 dispc.user_handler = NULL; in dispc_free_irq()
3880 dispc.user_data = NULL; in dispc_free_irq()
3892 dispc.pdev = pdev; in omap_dispchw_probe()
3894 spin_lock_init(&dispc.control_lock); in omap_dispchw_probe()
3896 r = dispc_init_features(dispc.pdev); in omap_dispchw_probe()
3900 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); in omap_dispchw_probe()
3906 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, in omap_dispchw_probe()
3908 if (!dispc.base) { in omap_dispchw_probe()
3913 dispc.irq = platform_get_irq(dispc.pdev, 0); in omap_dispchw_probe()
3914 if (dispc.irq < 0) { in omap_dispchw_probe()
3920 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in omap_dispchw_probe()
3921 if (IS_ERR(dispc.syscon_pol)) { in omap_dispchw_probe()
3923 return PTR_ERR(dispc.syscon_pol); in omap_dispchw_probe()
3927 &dispc.syscon_pol_offset)) { in omap_dispchw_probe()
3969 dispc.is_enabled = false; in dispc_runtime_suspend()
3973 synchronize_irq(dispc.irq); in dispc_runtime_suspend()
3994 dispc.is_enabled = true; in dispc_runtime_resume()