Lines Matching refs:DSI_CLK_CTRL
71 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) macro
1326 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor()
1329 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); in dsi_set_lp_clk_divisor()
1339 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ in dsi_enable_scp_clk()
1348 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ in dsi_disable_scp_clk()
1369 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power()
1372 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { in dsi_pll_power()
1676 DUMPREG(DSI_CLK_CTRL); in dsi_dump_dsidev_regs()
2148 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ in dsi_cio_init()
2172 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, in dsi_cio_init()
2183 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ in dsi_cio_init()
2200 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); in dsi_cio_uninit()
3142 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { in dsi_enter_ulps()
3144 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); in dsi_enter_ulps()
3495 r = dsi_read_reg(dsidev, DSI_CLK_CTRL); in dsi_config_cmd_mode_interleaving()