Lines Matching refs:reg
121 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg) in vgaHWRestore() argument
125 VGAwMISC(reg->MiscOutReg, par); in vgaHWRestore()
128 VGAwSEQ(i, reg->Sequencer[i], par); in vgaHWRestore()
132 VGAwCR(17, reg->CRTC[17] & ~0x80, par); in vgaHWRestore()
135 VGAwCR(i, reg->CRTC[i], par); in vgaHWRestore()
138 VGAwGR(i, reg->Graphics[i], par); in vgaHWRestore()
143 VGAwATTR(i, reg->Attribute[i], par); in vgaHWRestore()
151 struct savage_reg *reg) in vgaHWInit() argument
153 reg->MiscOutReg = 0x23; in vgaHWInit()
156 reg->MiscOutReg |= 0x40; in vgaHWInit()
159 reg->MiscOutReg |= 0x80; in vgaHWInit()
164 reg->Sequencer[0x00] = 0x00; in vgaHWInit()
165 reg->Sequencer[0x01] = 0x01; in vgaHWInit()
166 reg->Sequencer[0x02] = 0x0F; in vgaHWInit()
167 reg->Sequencer[0x03] = 0x00; /* Font select */ in vgaHWInit()
168 reg->Sequencer[0x04] = 0x0E; /* Misc */ in vgaHWInit()
173 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; in vgaHWInit()
174 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; in vgaHWInit()
175 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; in vgaHWInit()
176 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; in vgaHWInit()
177 reg->CRTC[0x04] = (timings->HSyncStart >> 3); in vgaHWInit()
178 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | in vgaHWInit()
180 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; in vgaHWInit()
181 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | in vgaHWInit()
189 reg->CRTC[0x08] = 0x00; in vgaHWInit()
190 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40; in vgaHWInit()
193 reg->CRTC[0x09] |= 0x80; in vgaHWInit()
195 reg->CRTC[0x0a] = 0x00; in vgaHWInit()
196 reg->CRTC[0x0b] = 0x00; in vgaHWInit()
197 reg->CRTC[0x0c] = 0x00; in vgaHWInit()
198 reg->CRTC[0x0d] = 0x00; in vgaHWInit()
199 reg->CRTC[0x0e] = 0x00; in vgaHWInit()
200 reg->CRTC[0x0f] = 0x00; in vgaHWInit()
201 reg->CRTC[0x10] = timings->VSyncStart & 0xff; in vgaHWInit()
202 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20; in vgaHWInit()
203 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff; in vgaHWInit()
204 reg->CRTC[0x13] = var->xres_virtual >> 4; in vgaHWInit()
205 reg->CRTC[0x14] = 0x00; in vgaHWInit()
206 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff; in vgaHWInit()
207 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff; in vgaHWInit()
208 reg->CRTC[0x17] = 0xc3; in vgaHWInit()
209 reg->CRTC[0x18] = 0xff; in vgaHWInit()
220 reg->Graphics[0x00] = 0x00; in vgaHWInit()
221 reg->Graphics[0x01] = 0x00; in vgaHWInit()
222 reg->Graphics[0x02] = 0x00; in vgaHWInit()
223 reg->Graphics[0x03] = 0x00; in vgaHWInit()
224 reg->Graphics[0x04] = 0x00; in vgaHWInit()
225 reg->Graphics[0x05] = 0x40; in vgaHWInit()
226 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */ in vgaHWInit()
227 reg->Graphics[0x07] = 0x0F; in vgaHWInit()
228 reg->Graphics[0x08] = 0xFF; in vgaHWInit()
231 reg->Attribute[0x00] = 0x00; /* standard colormap translation */ in vgaHWInit()
232 reg->Attribute[0x01] = 0x01; in vgaHWInit()
233 reg->Attribute[0x02] = 0x02; in vgaHWInit()
234 reg->Attribute[0x03] = 0x03; in vgaHWInit()
235 reg->Attribute[0x04] = 0x04; in vgaHWInit()
236 reg->Attribute[0x05] = 0x05; in vgaHWInit()
237 reg->Attribute[0x06] = 0x06; in vgaHWInit()
238 reg->Attribute[0x07] = 0x07; in vgaHWInit()
239 reg->Attribute[0x08] = 0x08; in vgaHWInit()
240 reg->Attribute[0x09] = 0x09; in vgaHWInit()
241 reg->Attribute[0x0a] = 0x0A; in vgaHWInit()
242 reg->Attribute[0x0b] = 0x0B; in vgaHWInit()
243 reg->Attribute[0x0c] = 0x0C; in vgaHWInit()
244 reg->Attribute[0x0d] = 0x0D; in vgaHWInit()
245 reg->Attribute[0x0e] = 0x0E; in vgaHWInit()
246 reg->Attribute[0x0f] = 0x0F; in vgaHWInit()
247 reg->Attribute[0x10] = 0x41; in vgaHWInit()
248 reg->Attribute[0x11] = 0xFF; in vgaHWInit()
249 reg->Attribute[0x12] = 0x0F; in vgaHWInit()
250 reg->Attribute[0x13] = 0x00; in vgaHWInit()
251 reg->Attribute[0x14] = 0x00; in vgaHWInit()
544 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg) in savage_get_default_par() argument
574 reg->SR08 = vga_in8(0x3c5, par); in savage_get_default_par()
579 reg->CR31 = vga_in8(0x3d5, par); in savage_get_default_par()
581 reg->CR32 = vga_in8(0x3d5, par); in savage_get_default_par()
583 reg->CR34 = vga_in8(0x3d5, par); in savage_get_default_par()
585 reg->CR36 = vga_in8(0x3d5, par); in savage_get_default_par()
587 reg->CR3A = vga_in8(0x3d5, par); in savage_get_default_par()
589 reg->CR40 = vga_in8(0x3d5, par); in savage_get_default_par()
591 reg->CR42 = vga_in8(0x3d5, par); in savage_get_default_par()
593 reg->CR45 = vga_in8(0x3d5, par); in savage_get_default_par()
595 reg->CR50 = vga_in8(0x3d5, par); in savage_get_default_par()
597 reg->CR51 = vga_in8(0x3d5, par); in savage_get_default_par()
599 reg->CR53 = vga_in8(0x3d5, par); in savage_get_default_par()
601 reg->CR58 = vga_in8(0x3d5, par); in savage_get_default_par()
603 reg->CR60 = vga_in8(0x3d5, par); in savage_get_default_par()
605 reg->CR66 = vga_in8(0x3d5, par); in savage_get_default_par()
607 reg->CR67 = vga_in8(0x3d5, par); in savage_get_default_par()
609 reg->CR68 = vga_in8(0x3d5, par); in savage_get_default_par()
611 reg->CR69 = vga_in8(0x3d5, par); in savage_get_default_par()
613 reg->CR6F = vga_in8(0x3d5, par); in savage_get_default_par()
616 reg->CR33 = vga_in8(0x3d5, par); in savage_get_default_par()
618 reg->CR86 = vga_in8(0x3d5, par); in savage_get_default_par()
620 reg->CR88 = vga_in8(0x3d5, par); in savage_get_default_par()
622 reg->CR90 = vga_in8(0x3d5, par); in savage_get_default_par()
624 reg->CR91 = vga_in8(0x3d5, par); in savage_get_default_par()
626 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; in savage_get_default_par()
630 reg->CR3B = vga_in8(0x3d5, par); in savage_get_default_par()
632 reg->CR3C = vga_in8(0x3d5, par); in savage_get_default_par()
634 reg->CR43 = vga_in8(0x3d5, par); in savage_get_default_par()
636 reg->CR5D = vga_in8(0x3d5, par); in savage_get_default_par()
638 reg->CR5E = vga_in8(0x3d5, par); in savage_get_default_par()
640 reg->CR65 = vga_in8(0x3d5, par); in savage_get_default_par()
644 reg->SR0E = vga_in8(0x3c5, par); in savage_get_default_par()
646 reg->SR0F = vga_in8(0x3c5, par); in savage_get_default_par()
648 reg->SR10 = vga_in8(0x3c5, par); in savage_get_default_par()
650 reg->SR11 = vga_in8(0x3c5, par); in savage_get_default_par()
652 reg->SR12 = vga_in8(0x3c5, par); in savage_get_default_par()
654 reg->SR13 = vga_in8(0x3c5, par); in savage_get_default_par()
656 reg->SR29 = vga_in8(0x3c5, par); in savage_get_default_par()
659 reg->SR15 = vga_in8(0x3c5, par); in savage_get_default_par()
661 reg->SR30 = vga_in8(0x3c5, par); in savage_get_default_par()
663 reg->SR18 = vga_in8(0x3c5, par); in savage_get_default_par()
671 reg->SR54[i] = vga_in8(0x3c5, par); in savage_get_default_par()
684 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par); in savage_get_default_par()
685 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par); in savage_get_default_par()
686 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par); in savage_get_default_par()
687 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par); in savage_get_default_par()
697 struct savage_reg *reg) in savage_set_default_par() argument
727 vga_out8(0x3c5, reg->SR08, par); in savage_set_default_par()
732 vga_out8(0x3d5, reg->CR31, par); in savage_set_default_par()
734 vga_out8(0x3d5, reg->CR32, par); in savage_set_default_par()
736 vga_out8(0x3d5, reg->CR34, par); in savage_set_default_par()
738 vga_out8(0x3d5,reg->CR36, par); in savage_set_default_par()
740 vga_out8(0x3d5, reg->CR3A, par); in savage_set_default_par()
742 vga_out8(0x3d5, reg->CR40, par); in savage_set_default_par()
744 vga_out8(0x3d5, reg->CR42, par); in savage_set_default_par()
746 vga_out8(0x3d5, reg->CR45, par); in savage_set_default_par()
748 vga_out8(0x3d5, reg->CR50, par); in savage_set_default_par()
750 vga_out8(0x3d5, reg->CR51, par); in savage_set_default_par()
752 vga_out8(0x3d5, reg->CR53, par); in savage_set_default_par()
754 vga_out8(0x3d5, reg->CR58, par); in savage_set_default_par()
756 vga_out8(0x3d5, reg->CR60, par); in savage_set_default_par()
758 vga_out8(0x3d5, reg->CR66, par); in savage_set_default_par()
760 vga_out8(0x3d5, reg->CR67, par); in savage_set_default_par()
762 vga_out8(0x3d5, reg->CR68, par); in savage_set_default_par()
764 vga_out8(0x3d5, reg->CR69, par); in savage_set_default_par()
766 vga_out8(0x3d5, reg->CR6F, par); in savage_set_default_par()
769 vga_out8(0x3d5, reg->CR33, par); in savage_set_default_par()
771 vga_out8(0x3d5, reg->CR86, par); in savage_set_default_par()
773 vga_out8(0x3d5, reg->CR88, par); in savage_set_default_par()
775 vga_out8(0x3d5, reg->CR90, par); in savage_set_default_par()
777 vga_out8(0x3d5, reg->CR91, par); in savage_set_default_par()
779 vga_out8(0x3d5, reg->CRB0, par); in savage_set_default_par()
783 vga_out8(0x3d5, reg->CR3B, par); in savage_set_default_par()
785 vga_out8(0x3d5, reg->CR3C, par); in savage_set_default_par()
787 vga_out8(0x3d5, reg->CR43, par); in savage_set_default_par()
789 vga_out8(0x3d5, reg->CR5D, par); in savage_set_default_par()
791 vga_out8(0x3d5, reg->CR5E, par); in savage_set_default_par()
793 vga_out8(0x3d5, reg->CR65, par); in savage_set_default_par()
797 vga_out8(0x3c5, reg->SR0E, par); in savage_set_default_par()
799 vga_out8(0x3c5, reg->SR0F, par); in savage_set_default_par()
801 vga_out8(0x3c5, reg->SR10, par); in savage_set_default_par()
803 vga_out8(0x3c5, reg->SR11, par); in savage_set_default_par()
805 vga_out8(0x3c5, reg->SR12, par); in savage_set_default_par()
807 vga_out8(0x3c5, reg->SR13, par); in savage_set_default_par()
809 vga_out8(0x3c5, reg->SR29, par); in savage_set_default_par()
812 vga_out8(0x3c5, reg->SR15, par); in savage_set_default_par()
814 vga_out8(0x3c5, reg->SR30, par); in savage_set_default_par()
816 vga_out8(0x3c5, reg->SR18, par); in savage_set_default_par()
824 vga_out8(0x3c5, reg->SR54[i], par); in savage_set_default_par()
837 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); in savage_set_default_par()
838 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); in savage_set_default_par()
839 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); in savage_set_default_par()
840 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); in savage_set_default_par()
975 struct savage_reg *reg) in savagefb_decode_var() argument
1017 vgaHWInit(var, par, &timings, reg); in savagefb_decode_var()
1022 reg->CR67 = 0x00; in savagefb_decode_var()
1027 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ in savagefb_decode_var()
1029 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ in savagefb_decode_var()
1034 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ in savagefb_decode_var()
1036 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ in savagefb_decode_var()
1041 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ in savagefb_decode_var()
1043 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ in savagefb_decode_var()
1046 reg->CR67 = 0x70; in savagefb_decode_var()
1049 reg->CR67 = 0xd0; in savagefb_decode_var()
1061 reg->CR3A = (tmp & 0x7f) | 0x15; in savagefb_decode_var()
1063 reg->CR3A = tmp | 0x95; in savagefb_decode_var()
1065 reg->CR53 = 0x00; in savagefb_decode_var()
1066 reg->CR31 = 0x8c; in savagefb_decode_var()
1067 reg->CR66 = 0x89; in savagefb_decode_var()
1070 reg->CR58 = vga_in8(0x3d5, par) & 0x80; in savagefb_decode_var()
1071 reg->CR58 |= 0x13; in savagefb_decode_var()
1073 reg->SR15 = 0x03 | 0x80; in savagefb_decode_var()
1074 reg->SR18 = 0x00; in savagefb_decode_var()
1075 reg->CR43 = reg->CR45 = reg->CR65 = 0x00; in savagefb_decode_var()
1078 reg->CR40 = vga_in8(0x3d5, par) & ~0x01; in savagefb_decode_var()
1080 reg->MMPR0 = 0x010400; in savagefb_decode_var()
1081 reg->MMPR1 = 0x00; in savagefb_decode_var()
1082 reg->MMPR2 = 0x0808; in savagefb_decode_var()
1083 reg->MMPR3 = 0x08080810; in savagefb_decode_var()
1089 reg->SR10 = 255; in savagefb_decode_var()
1090 reg->SR11 = 255; in savagefb_decode_var()
1093 ®->SR11, ®->SR10); in savagefb_decode_var()
1098 reg->SR12 = (r << 6) | (n & 0x3f); in savagefb_decode_var()
1099 reg->SR13 = m & 0xff; in savagefb_decode_var()
1100 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2; in savagefb_decode_var()
1103 reg->MMPR0 -= 0x8000; in savagefb_decode_var()
1105 reg->MMPR0 -= 0x4000; in savagefb_decode_var()
1108 reg->CR42 = 0x20; in savagefb_decode_var()
1110 reg->CR42 = 0x00; in savagefb_decode_var()
1112 reg->CR34 = 0x10; /* display fifo */ in savagefb_decode_var()
1124 j = (reg->CRTC[0] + ((i & 0x01) << 8) + in savagefb_decode_var()
1125 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2; in savagefb_decode_var()
1127 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) { in savagefb_decode_var()
1128 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <= in savagefb_decode_var()
1129 reg->CRTC[0] + ((i & 0x01) << 8)) in savagefb_decode_var()
1130 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4; in savagefb_decode_var()
1132 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1; in savagefb_decode_var()
1135 reg->CR3B = j & 0xff; in savagefb_decode_var()
1137 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2; in savagefb_decode_var()
1138 reg->CR5D = i; in savagefb_decode_var()
1139 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) | in savagefb_decode_var()
1144 reg->CR91 = reg->CRTC[19] = 0xff & width; in savagefb_decode_var()
1145 reg->CR51 = (0x300 & width) >> 4; in savagefb_decode_var()
1146 reg->CR90 = 0x80 | (width >> 8); in savagefb_decode_var()
1147 reg->MiscOutReg |= 0x0c; in savagefb_decode_var()
1152 reg->CR50 = 0; in savagefb_decode_var()
1154 reg->CR50 = 0x10; in savagefb_decode_var()
1156 reg->CR50 = 0x30; in savagefb_decode_var()
1159 reg->CR50 |= 0x40; in savagefb_decode_var()
1161 reg->CR50 |= 0x80; in savagefb_decode_var()
1163 reg->CR50 |= 0x00; in savagefb_decode_var()
1165 reg->CR50 |= 0x01; in savagefb_decode_var()
1167 reg->CR50 |= 0xc0; in savagefb_decode_var()
1169 reg->CR50 |= 0x81; in savagefb_decode_var()
1171 reg->CR50 |= 0xc1; /* Use GBD */ in savagefb_decode_var()
1174 reg->CR33 = 0x08; in savagefb_decode_var()
1176 reg->CR33 = 0x20; in savagefb_decode_var()
1178 reg->CRTC[0x17] = 0xeb; in savagefb_decode_var()
1180 reg->CR67 |= 1; in savagefb_decode_var()
1183 reg->CR36 = vga_in8(0x3d5, par); in savagefb_decode_var()
1185 reg->CR68 = vga_in8(0x3d5, par); in savagefb_decode_var()
1186 reg->CR69 = 0; in savagefb_decode_var()
1188 reg->CR6F = vga_in8(0x3d5, par); in savagefb_decode_var()
1190 reg->CR86 = vga_in8(0x3d5, par); in savagefb_decode_var()
1192 reg->CR88 = vga_in8(0x3d5, par) | 0x08; in savagefb_decode_var()
1194 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; in savagefb_decode_var()
1261 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg) in savagefb_set_par_int() argument
1296 vga_out8(0x3d5, reg->CR66, par); in savagefb_set_par_int()
1298 vga_out8(0x3d5, reg->CR3A, par); in savagefb_set_par_int()
1300 vga_out8(0x3d5, reg->CR31, par); in savagefb_set_par_int()
1302 vga_out8(0x3d5, reg->CR32, par); in savagefb_set_par_int()
1304 vga_out8(0x3d5, reg->CR58, par); in savagefb_set_par_int()
1306 vga_out8(0x3d5, reg->CR53 & 0x7f, par); in savagefb_set_par_int()
1313 vga_out8(0x3c5, reg->SR0E, par); in savagefb_set_par_int()
1315 vga_out8(0x3c5, reg->SR0F, par); in savagefb_set_par_int()
1317 vga_out8(0x3c5, reg->SR29, par); in savagefb_set_par_int()
1319 vga_out8(0x3c5, reg->SR15, par); in savagefb_set_par_int()
1327 vga_out8(0x3c5, reg->SR54[i], par); in savagefb_set_par_int()
1331 vgaHWRestore (par, reg); in savagefb_set_par_int()
1335 vga_out8(0x3d5, reg->CR53, par); in savagefb_set_par_int()
1337 vga_out8(0x3d5, reg->CR5D, par); in savagefb_set_par_int()
1339 vga_out8(0x3d5, reg->CR5E, par); in savagefb_set_par_int()
1341 vga_out8(0x3d5, reg->CR3B, par); in savagefb_set_par_int()
1343 vga_out8(0x3d5, reg->CR3C, par); in savagefb_set_par_int()
1345 vga_out8(0x3d5, reg->CR43, par); in savagefb_set_par_int()
1347 vga_out8(0x3d5, reg->CR65, par); in savagefb_set_par_int()
1357 vga_out8(0x3d5, reg->CR67 & ~0x0c, par); in savagefb_set_par_int()
1361 vga_out8(0x3d5, reg->CR34, par); in savagefb_set_par_int()
1363 vga_out8(0x3d5, reg->CR40, par); in savagefb_set_par_int()
1365 vga_out8(0x3d5, reg->CR42, par); in savagefb_set_par_int()
1367 vga_out8(0x3d5, reg->CR45, par); in savagefb_set_par_int()
1369 vga_out8(0x3d5, reg->CR50, par); in savagefb_set_par_int()
1371 vga_out8(0x3d5, reg->CR51, par); in savagefb_set_par_int()
1375 vga_out8(0x3d5, reg->CR36, par); in savagefb_set_par_int()
1377 vga_out8(0x3d5, reg->CR60, par); in savagefb_set_par_int()
1379 vga_out8(0x3d5, reg->CR68, par); in savagefb_set_par_int()
1381 vga_out8(0x3d5, reg->CR69, par); in savagefb_set_par_int()
1383 vga_out8(0x3d5, reg->CR6F, par); in savagefb_set_par_int()
1386 vga_out8(0x3d5, reg->CR33, par); in savagefb_set_par_int()
1388 vga_out8(0x3d5, reg->CR86, par); in savagefb_set_par_int()
1390 vga_out8(0x3d5, reg->CR88, par); in savagefb_set_par_int()
1392 vga_out8(0x3d5, reg->CR90, par); in savagefb_set_par_int()
1394 vga_out8(0x3d5, reg->CR91, par); in savagefb_set_par_int()
1398 vga_out8(0x3d5, reg->CRB0, par); in savagefb_set_par_int()
1402 vga_out8(0x3d5, reg->CR32, par); in savagefb_set_par_int()
1411 if (reg->SR10 != 255) { in savagefb_set_par_int()
1413 vga_out8(0x3c5, reg->SR10, par); in savagefb_set_par_int()
1415 vga_out8(0x3c5, reg->SR11, par); in savagefb_set_par_int()
1420 vga_out8(0x3c5, reg->SR0E, par); in savagefb_set_par_int()
1422 vga_out8(0x3c5, reg->SR0F, par); in savagefb_set_par_int()
1424 vga_out8(0x3c5, reg->SR12, par); in savagefb_set_par_int()
1426 vga_out8(0x3c5, reg->SR13, par); in savagefb_set_par_int()
1428 vga_out8(0x3c5, reg->SR29, par); in savagefb_set_par_int()
1430 vga_out8(0x3c5, reg->SR18, par); in savagefb_set_par_int()
1439 vga_out8(0x3c5, reg->SR15, par); in savagefb_set_par_int()
1443 vga_out8(0x3c5, reg->SR30, par); in savagefb_set_par_int()
1445 vga_out8(0x3c5, reg->SR08, par); in savagefb_set_par_int()
1450 vga_out8(0x3d5, reg->CR67, par); in savagefb_set_par_int()
1461 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); in savagefb_set_par_int()
1463 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); in savagefb_set_par_int()
1465 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); in savagefb_set_par_int()
1467 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); in savagefb_set_par_int()