85 	iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);  in sh_mipi_send_short()
86 	iowrite32(1, mipi->linkbase + CMTSRTREQ);  in sh_mipi_send_short()
120 	iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);  in sh_mipi_dsi_enable()
225 	iowrite32(0x00000001, base + SYSCTRL);  in sh_mipi_setup()
228 	iowrite32(0x00000000, base + SYSCTRL);  in sh_mipi_setup()
239 	iowrite32(0x70003332, base + TIMSET);  in sh_mipi_setup()
241 	iowrite32(0x00000000, base + RESREQSET0);  in sh_mipi_setup()
243 	iowrite32(0x00000100, base + RESREQSET1);  in sh_mipi_setup()
245 	iowrite32(0x0fffffff, base + HSTTOVSET);  in sh_mipi_setup()
247 	iowrite32(0x0fffffff, base + LPRTOVSET);  in sh_mipi_setup()
249 	iowrite32(0x0fffffff, base + TATOVSET);  in sh_mipi_setup()
251 	iowrite32(0x0fffffff, base + PRTOVSET);  in sh_mipi_setup()
253 	iowrite32(0, base + DSIINTE);  in sh_mipi_setup()
255 	iowrite32(0x00000001, base + PHYCTRL);  in sh_mipi_setup()
258 	iowrite32(0x03070001 | pdata->phyctrl, base + PHYCTRL);  in sh_mipi_setup()
269 	iowrite32(tmp, base + SYSCONF);  in sh_mipi_setup()
277 	iowrite32(0x00000006, mipi->linkbase + DTCTR);  in sh_mipi_setup()
279 	iowrite32((mode->vsync_len << pdata->vsynw_offset) |  in sh_mipi_setup()
302 	iowrite32(vmctr2, mipi->linkbase + VMCTR2);  in sh_mipi_setup()
314 	iowrite32(top | bottom , mipi->linkbase + VMLEN1);  in sh_mipi_setup()
348 	iowrite32(top | (bottom + delay) , mipi->linkbase + VMLEN2);  in sh_mipi_setup()
374 	iowrite32(0x00000f00, base + DSICTRL);  in sh_mipi_setup()