969 	union pll_cntl_u pll_cntl;  member
1073 	w100_pwr_state.pll_cntl.f.pll_pwdn = 0x0;     /* power down */  in w100_pll_adjust()
1074 	w100_pwr_state.pll_cntl.f.pll_reset = 0x0;    /* not reset */  in w100_pll_adjust()
1075 	w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x1;   /* Hi-Z */  in w100_pll_adjust()
1076 	w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;      /* VCO gain = 0 */  in w100_pll_adjust()
1077 	w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0;    /* VCO frequency range control = off */  in w100_pll_adjust()
1078 	w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;  /* current offset inside VCO = 0 */  in w100_pll_adjust()
1079 	w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;  in w100_pll_adjust()
1087 		w100_pwr_state.pll_cntl.f.pll_dactal = 0xd;  in w100_pll_adjust()
1088 		writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_adjust()
1093 			w100_pwr_state.pll_cntl.f.pll_dactal = 0x7;  in w100_pll_adjust()
1094 			writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_adjust()
1100 			if ((w100_pwr_state.pll_cntl.f.pll_vcofr == 0x0) &&  in w100_pll_adjust()
1101 				((w100_pwr_state.pll_cntl.f.pll_pvg == 0x7) ||  in w100_pll_adjust()
1102 				(w100_pwr_state.pll_cntl.f.pll_ioffset == 0x0))) {  in w100_pll_adjust()
1104 				w100_pwr_state.pll_cntl.f.pll_vcofr = 0x1;  in w100_pll_adjust()
1105 				w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;  in w100_pll_adjust()
1106 				w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;  in w100_pll_adjust()
1110 		if ((w100_pwr_state.pll_cntl.f.pll_ioffset) < 0x3) {  in w100_pll_adjust()
1111 			w100_pwr_state.pll_cntl.f.pll_ioffset += 0x1;  in w100_pll_adjust()
1112 		} else if ((w100_pwr_state.pll_cntl.f.pll_pvg) < 0x7) {  in w100_pll_adjust()
1113 			w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;  in w100_pll_adjust()
1114 			w100_pwr_state.pll_cntl.f.pll_pvg += 0x1;  in w100_pll_adjust()
1133 	w100_pwr_state.pll_cntl.f.pll_dactal = 0xa;  in w100_pll_calibration()
1134 	writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_calibration()
1139 	w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0;  /* normal */  in w100_pll_calibration()
1140 	writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_calibration()
1143 	w100_pwr_state.pll_cntl.f.pll_dactal = 0x0;  in w100_pll_calibration()
1144 	writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_calibration()
1247 	w100_pwr_state.pll_cntl.f.pll_pwdn = 0x1;  in w100_pwm_setup()
1248 	w100_pwr_state.pll_cntl.f.pll_reset = 0x1;  in w100_pwm_setup()
1249 	w100_pwr_state.pll_cntl.f.pll_pm_en = 0x0;  in w100_pwm_setup()
1250 	w100_pwr_state.pll_cntl.f.pll_mode = 0x0;  /* uses VCO clock */  in w100_pwm_setup()
1251 	w100_pwr_state.pll_cntl.f.pll_refclk_sel = 0x0;  in w100_pwm_setup()
1252 	w100_pwr_state.pll_cntl.f.pll_fbclk_sel = 0x0;  in w100_pwm_setup()
1253 	w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0;  in w100_pwm_setup()
1254 	w100_pwr_state.pll_cntl.f.pll_pcp = 0x4;  in w100_pwm_setup()
1255 	w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;  in w100_pwm_setup()
1256 	w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0;  in w100_pwm_setup()
1257 	w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;  in w100_pwm_setup()
1258 	w100_pwr_state.pll_cntl.f.pll_pecc_mode = 0x0;  in w100_pwm_setup()
1259 	w100_pwr_state.pll_cntl.f.pll_pecc_scon = 0x0;  in w100_pwm_setup()
1260 	w100_pwr_state.pll_cntl.f.pll_dactal = 0x0;  /* Hi-Z */  in w100_pwm_setup()
1261 	w100_pwr_state.pll_cntl.f.pll_cp_clip = 0x3;  in w100_pwm_setup()
1262 	w100_pwr_state.pll_cntl.f.pll_conf = 0x2;  in w100_pwm_setup()
1263 	w100_pwr_state.pll_cntl.f.pll_mbctrl = 0x2;  in w100_pwm_setup()
1264 	w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;  in w100_pwm_setup()
1265 	writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pwm_setup()