159 	iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_PERR_irqhandler()
208 	iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
311 	iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);  in tsi148_irqhandler()
376 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_init()
377 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_init()
388 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_exit()
389 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_exit()
392 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);  in tsi148_irq_exit()
429 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
433 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
442 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
446 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
470 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
474 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
626 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
630 	iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
632 	iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
634 	iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
636 	iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
638 	iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
640 	iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
685 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
691 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
992 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1094 	iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1096 	iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1098 	iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1100 	iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1102 	iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1104 	iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1108 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1114 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1477 	iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);  in tsi148_master_rmw()
1478 	iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);  in tsi148_master_rmw()
1479 	iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);  in tsi148_master_rmw()
1480 	iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);  in tsi148_master_rmw()
1481 	iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);  in tsi148_master_rmw()
1486 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1494 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1932 	iowrite32be(bus_addr_high, bridge->base +  in tsi148_dma_list_exec()
1934 	iowrite32be(bus_addr_low, bridge->base +  in tsi148_dma_list_exec()
1941 	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +  in tsi148_dma_list_exec()
2054 	iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_set()
2055 	iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_set()
2056 	iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_set()
2152 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2156 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2161 		iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2184 	iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2188 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2190 	iowrite32be(TSI148_LCSR_INTC_LMC[monitor],  in tsi148_lm_detach()
2201 		iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2283 	iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_init()
2284 	iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_init()
2295 		iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2304 		iowrite32be(crat | TSI148_LCSR_CRAT_EN,  in tsi148_crcsr_init()
2335 	iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,  in tsi148_crcsr_exit()
2339 	iowrite32be(0, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_exit()
2340 	iowrite32be(0, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_exit()
2600 	iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);  in tsi148_probe()
2674 		iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_remove()
2676 		iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_remove()
2683 	iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);  in tsi148_remove()
2688 	iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);  in tsi148_remove()
2693 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_remove()
2694 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);  in tsi148_remove()
2695 	iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);  in tsi148_remove()
2701 		iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);  in tsi148_remove()
2706 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);  in tsi148_remove()
2707 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);  in tsi148_remove()