78 	u32 val;  in tco_timer_start()  local
82 	val = readl(SP5100_WDT_CONTROL(tcobase));  in tco_timer_start()
83 	val |= SP5100_WDT_START_STOP_BIT;  in tco_timer_start()
84 	writel(val, SP5100_WDT_CONTROL(tcobase));  in tco_timer_start()
90 	u32 val;  in tco_timer_stop()  local
94 	val = readl(SP5100_WDT_CONTROL(tcobase));  in tco_timer_stop()
95 	val &= ~SP5100_WDT_START_STOP_BIT;  in tco_timer_stop()
96 	writel(val, SP5100_WDT_CONTROL(tcobase));  in tco_timer_stop()
102 	u32 val;  in tco_timer_keepalive()  local
106 	val = readl(SP5100_WDT_CONTROL(tcobase));  in tco_timer_keepalive()
107 	val |= SP5100_WDT_TRIGGER_BIT;  in tco_timer_keepalive()
108 	writel(val, SP5100_WDT_CONTROL(tcobase));  in tco_timer_keepalive()
130 	int val;  in tco_timer_enable()  local
136 		val = inb(SB800_IO_PM_DATA_REG);  in tco_timer_enable()
137 		val |= SB800_PM_WATCHDOG_SECOND_RES;  in tco_timer_enable()
138 		outb(val, SB800_IO_PM_DATA_REG);  in tco_timer_enable()
142 		val = inb(SB800_IO_PM_DATA_REG);  in tco_timer_enable()
143 		val |= SB800_PCI_WATCHDOG_DECODE_EN;  in tco_timer_enable()
144 		val &= ~SB800_PM_WATCHDOG_DISABLE;  in tco_timer_enable()
145 		outb(val, SB800_IO_PM_DATA_REG);  in tco_timer_enable()
151 				      &val);  in tco_timer_enable()
153 		val |= SP5100_PCI_WATCHDOG_DECODE_EN;  in tco_timer_enable()
157 				       val);  in tco_timer_enable()
161 		val = inb(SP5100_IO_PM_DATA_REG);  in tco_timer_enable()
162 		val |= SP5100_PM_WATCHDOG_SECOND_RES;  in tco_timer_enable()
163 		val &= ~SP5100_PM_WATCHDOG_DISABLE;  in tco_timer_enable()
164 		outb(val, SP5100_IO_PM_DATA_REG);  in tco_timer_enable()
320 	u32 val;  in sp5100_tco_setupdevice()  local
362 	val = inb(data_reg);  in sp5100_tco_setupdevice()
364 	val = val << 8 | inb(data_reg);  in sp5100_tco_setupdevice()
366 	val = val << 8 | inb(data_reg);  in sp5100_tco_setupdevice()
369 	val = val << 8 | (inb(data_reg) & 0xf8);  in sp5100_tco_setupdevice()
371 	pr_debug("Got 0x%04x from indirect I/O\n", val);  in sp5100_tco_setupdevice()
374 	if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,  in sp5100_tco_setupdevice()
378 		pr_debug("MMIO address 0x%04x already in use\n", val);  in sp5100_tco_setupdevice()
387 		val = inb(SB800_IO_PM_DATA_REG);  in sp5100_tco_setupdevice()
389 		val = val << 8 | inb(SB800_IO_PM_DATA_REG);  in sp5100_tco_setupdevice()
391 		val = val << 8 | inb(SB800_IO_PM_DATA_REG);  in sp5100_tco_setupdevice()
393 		val = val << 8 | inb(SB800_IO_PM_DATA_REG);  in sp5100_tco_setupdevice()
397 				      SP5100_SB_RESOURCE_MMIO_BASE, &val);  in sp5100_tco_setupdevice()
401 	if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) ==  in sp5100_tco_setupdevice()
404 		val &= ~0xFFF;  in sp5100_tco_setupdevice()
406 		val += SB800_PM_WDT_MMIO_OFFSET;  in sp5100_tco_setupdevice()
408 		if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,  in sp5100_tco_setupdevice()
411 				val);  in sp5100_tco_setupdevice()
414 			pr_debug("MMIO address 0x%04x already in use\n", val);  in sp5100_tco_setupdevice()
416 		pr_debug("SBResource_MMIO is disabled(0x%04x)\n", val);  in sp5100_tco_setupdevice()
422 	tcobase_phys = val;  in sp5100_tco_setupdevice()
424 	tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);  in sp5100_tco_setupdevice()
430 	pr_info("Using 0x%04x for watchdog MMIO address\n", val);  in sp5100_tco_setupdevice()
436 	val = readl(SP5100_WDT_CONTROL(tcobase));  in sp5100_tco_setupdevice()
441 	tco_wdt_fired = val & SP5100_PM_WATCHDOG_FIRED;  in sp5100_tco_setupdevice()
442 	val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;  in sp5100_tco_setupdevice()
443 	writel(val, SP5100_WDT_CONTROL(tcobase));  in sp5100_tco_setupdevice()