101 #define rtsx_pci_writel(pcr, reg, value) \  argument
103 #define rtsx_pci_readl(pcr, reg) \  argument
105 #define rtsx_pci_writew(pcr, reg, value) \  argument
107 #define rtsx_pci_readw(pcr, reg) \  argument
109 #define rtsx_pci_writeb(pcr, reg, value) \  argument
111 #define rtsx_pci_readb(pcr, reg) \  argument
114 #define rtsx_pci_read_config_byte(pcr, where, val) \  argument
117 #define rtsx_pci_write_config_byte(pcr, where, val) \  argument
120 #define rtsx_pci_read_config_dword(pcr, where, val) \  argument
123 #define rtsx_pci_write_config_dword(pcr, where, val) \  argument
845 #define rtsx_pci_init_cmd(pcr)		((pcr)->ci = 0)  argument
850 	struct rtsx_pcr			*pcr;  member
956 #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))  argument
957 #define PCI_VID(pcr)			((pcr)->pci->vendor)  argument
958 #define PCI_PID(pcr)			((pcr)->pci->device)  argument
959 #define is_version(pcr, pid, ver)				\  argument
961 #define pcr_dbg(pcr, fmt, arg...)				\  argument
967 #define SDR104_TX_PHASE(pcr)		SDR104_PHASE((pcr)->tx_initial_phase)  argument
968 #define SDR50_TX_PHASE(pcr)		SDR50_PHASE((pcr)->tx_initial_phase)  argument
969 #define DDR50_TX_PHASE(pcr)		DDR50_PHASE((pcr)->tx_initial_phase)  argument
970 #define SDR104_RX_PHASE(pcr)		SDR104_PHASE((pcr)->rx_initial_phase)  argument
971 #define SDR50_RX_PHASE(pcr)		SDR50_PHASE((pcr)->rx_initial_phase)  argument
972 #define DDR50_RX_PHASE(pcr)		DDR50_PHASE((pcr)->rx_initial_phase)  argument
1007 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)  in rtsx_pci_get_cmd_data()
1012 static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,  in rtsx_pci_update_cfg_byte()
1024 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)  in rtsx_pci_write_be32()
1032 static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,  in rtsx_pci_update_phy()