Lines Matching refs:V4L2_DV_VSYNC_POS_POL
82 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
91 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
99 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
108 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
116 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
125 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
134 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
142 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
151 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
160 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
168 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
178 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
187 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
196 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
204 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
213 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
221 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
230 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
239 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
247 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
256 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
264 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
282 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
289 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
322 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
330 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
338 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
346 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
354 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
370 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
378 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
401 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
409 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
426 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
444 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
451 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
458 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
481 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
488 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
495 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
511 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
519 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
536 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
544 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
552 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
568 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
584 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
592 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
608 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
615 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
622 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
646 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
653 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
660 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
676 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
685 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
693 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
701 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
709 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
717 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
741 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
748 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
755 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
770 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
777 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
792 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
799 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
825 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
832 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
839 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
854 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
861 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
877 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
893 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
900 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
907 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \