Lines Matching refs:azx_readl
64 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); in azx_stream_start()
86 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); in azx_stream_stop()
156 if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE)) in azx_setup_controller()
223 return azx_readl(chip, WALLCLK); in azx_cc_read()
605 azx_readl(chip, OLD_SSYNC) | sbits); in azx_pcm_trigger()
607 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); in azx_pcm_trigger()
614 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); in azx_pcm_trigger()
662 azx_readl(chip, OLD_SSYNC) & ~sbits); in azx_pcm_trigger()
664 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); in azx_pcm_trigger()
1252 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL); in azx_rirb_get_response()
1275 chip->rirb.res[addr] = azx_readl(chip, IR); in azx_single_wait_for_response()
1525 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET); in azx_enter_link_reset()
1579 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | in azx_reset()
1596 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | in azx_int_enable()
1617 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & in azx_int_disable()
1713 status = azx_readl(chip, INTSTS); in azx_interrupt()