63 	azx_writel(chip, INTCTL,  in azx_stream_start()
85 	azx_writel(chip, INTCTL,  in azx_stream_stop()
157 			azx_writel(chip, DPLBASE,  in azx_setup_controller()
604 		azx_writel(chip, OLD_SSYNC,  in azx_pcm_trigger()
607 		azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);  in azx_pcm_trigger()
661 		azx_writel(chip, OLD_SSYNC,  in azx_pcm_trigger()
664 		azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);  in azx_pcm_trigger()
1000 	azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);  in azx_init_cmd_io()
1001 	azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));  in azx_init_cmd_io()
1039 	azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);  in azx_init_cmd_io()
1040 	azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));  in azx_init_cmd_io()
1252 	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL);  in azx_rirb_get_response()
1301 			azx_writel(chip, IC, val);  in azx_single_send_cmd()
1525 	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET);  in azx_enter_link_reset()
1579 		azx_writel(chip, GCTL, azx_readl(chip, GCTL) |  in azx_reset()
1596 	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |  in azx_int_enable()
1617 	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &  in azx_int_disable()
1639 	azx_writel(chip, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);  in azx_int_clear()
1662 	azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);  in azx_init_chip()
1663 	azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));  in azx_init_chip()
1682 	azx_writel(chip, DPLBASE, 0);  in azx_stop_chip()
1683 	azx_writel(chip, DPUBASE, 0);  in azx_stop_chip()