302 	struct sst_hsw_ipc_dx_reply dx;  member
1427 	enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)  in sst_hsw_dx_set_state()  argument
1438 		sizeof(state_), dx, sizeof(*dx));  in sst_hsw_dx_set_state()
1444 	for (item = 0; item < dx->entries_no; item++) {  in sst_hsw_dx_set_state()
1447 			item, dx->mem_info[item].offset,  in sst_hsw_dx_set_state()
1448 			dx->mem_info[item].size,  in sst_hsw_dx_set_state()
1449 			dx->mem_info[item].source);  in sst_hsw_dx_set_state()
1452 		dx->entries_no, state);  in sst_hsw_dx_set_state()
1507 	if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {  in sst_hsw_dx_state_dump()
1511 		memset(&hsw->dx, 0, sizeof(hsw->dx));  in sst_hsw_dx_state_dump()
1526 	for (item = 0; item < hsw->dx.entries_no; item++) {  in sst_hsw_dx_state_dump()
1527 		if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP  in sst_hsw_dx_state_dump()
1528 			&& hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET  in sst_hsw_dx_state_dump()
1529 			&& hsw->dx.mem_info[item].offset <  in sst_hsw_dx_state_dump()
1532 			offset = hsw->dx.mem_info[item].offset  in sst_hsw_dx_state_dump()
1534 			size = (hsw->dx.mem_info[item].size + 3) & (~3);  in sst_hsw_dx_state_dump()
1541 				memset(&hsw->dx, 0, sizeof(hsw->dx));  in sst_hsw_dx_state_dump()
1558 	for (item = 0; item < hsw->dx.entries_no; item++) {  in sst_hsw_dx_state_restore()
1559 		if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP  in sst_hsw_dx_state_restore()
1560 			&& hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET  in sst_hsw_dx_state_restore()
1561 			&& hsw->dx.mem_info[item].offset <  in sst_hsw_dx_state_restore()
1564 			offset = hsw->dx.mem_info[item].offset  in sst_hsw_dx_state_restore()
1566 			size = (hsw->dx.mem_info[item].size + 3) & (~3);  in sst_hsw_dx_state_restore()
1650 	ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);  in sst_hsw_dsp_runtime_suspend()