Lines Matching refs:must

48 The device tree blob (dtb) must be placed on an 8-byte boundary and must
50 using blocks of up to 2 megabytes in size, it must not be placed within
51 any 2M region which must be mapped with any specific attributes.
101   little-endian and must be respected.  Where image_size is zero,
119 The Image must be placed text_offset bytes from a 2MB aligned base
126 At least image_size bytes from the start of the image must be free for
134 Before jumping into the kernel, the following conditions must be met:
147   All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
149   The CPU must be in either EL2 (RECOMMENDED in order to have access to
153   The MMU must be off.
155   The address range corresponding to the loaded kernel image must be
160   operations must be configured and may be enabled.
162   operations (not recommended) must be configured and disabled.
165   CNTFRQ must be programmed with the timer frequency and CNTVOFF must
167   kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
171   All CPUs to be booted by the kernel must be part of the same coherency
178   the kernel image will be entered must be initialised by software at a
183     ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
184     ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
186     ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
187     ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
188   - The DT or ACPI tables must describe a GICv3 interrupt controller.
193     ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
195     ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
196   - The DT or ACPI tables must describe a GICv2 interrupt controller.
199 timers, coherency and system registers apply to all CPUs.  All CPUs must
205 - The primary CPU must jump directly to the first instruction of the
206   kernel image.  The device tree blob passed by this CPU must contain
213 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
219   device tree) polling their cpu-release-addr location, which must be
223   cpu-release-addr returns a non-zero value, the CPU must jump to this
225   value, so CPUs must convert the read value to their native endianness