Lines Matching refs:PHY

10 the PHY specifier identifies the PHY and its meaning is as follows:
16 Samsung EXYNOS SoC series Display Port PHY
25 - #phy-cells : from the generic PHY bindings, must be 0;
27 Samsung S5P/EXYNOS SoC series USB PHY
45 	  PHY module
50 The first phandle argument in the PHY specifier identifies the PHY, its
77 Then the PHY can be used in other nodes such as:
84 Refer to DT bindings documentation of particular PHY consumer devices for more
87 Samsung SATA PHY Controller
90 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
91 Each SATA PHY controller should have its own node.
95 - reg : offset and length of the SATA PHY register set;
127 Samsung Exynos5 SoC series USB DRD PHY controller
136 - reg : Register offset and length of USB DRD PHY register set;
140 	- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
142 	- ref: PHY's reference clock (usually crystal clock), used for
143 	       PHY operations, associated by phy name. It is used to
153 - #phy-cells : from the generic PHY bindings, must be 1;
156 compatible PHYs, the second cell in the PHY specifier identifies the
157 PHY id, which is interpreted as follows:
171 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,