Lines Matching refs:A
117 { A == 1; B == 2 }
118 A = 3; x = B;
119 B = 4; y = A;
124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
159 (Q == &A) and (D == 1)
173 registers that are accessed through an address port register (A) and a data
177 *A = 5;
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
240 X = *A; Y = *B; *D = Z;
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
254 X = *A; Y = *(A + 4);
258 X = LOAD *A; Y = LOAD *(A + 4);
259 Y = LOAD *(A + 4); X = LOAD *A;
260 {X, Y} = LOAD {*A, *(A + 4) };
264 *A = X; *(A + 4) = Y;
268 STORE *A = X; STORE *(A + 4) = Y;
269 STORE *(A + 4) = Y; STORE *A = X;
270 STORE {*A, *(A + 4) } = {X, Y};
305 NOTE 2: A bit-field and an adjacent non-bit-field member
344 A write memory barrier gives a guarantee that all the STORE operations
349 A write barrier is a partial ordering on stores only; it is not required
352 A CPU can be viewed as committing a sequence of store operations to the
362 A data dependency barrier is a weaker form of read barrier. In the case
369 A data dependency barrier is a partial ordering on interdependent loads
375 considered can then perceive. A data dependency barrier issued by the CPU
398 A read barrier is a data dependency barrier plus a guarantee that all the
403 A read barrier is a partial ordering on loads only; it is not required to
415 A general memory barrier gives a guarantee that all the LOAD and STORE
420 A general memory barrier is a partial ordering over both loads and stores.
520 { A == 1, B == 2, C = 3, P == &A, Q == &C }
528 sequence, Q must be either &A or &B, and that:
530 (Q == &A) implies (D == 1)
547 { A == 1, B == 2, C = 3, P == &A, Q == &C }
595 A load-load control dependency requires a full read memory barrier, not
829 always be paired. A lack of appropriate pairing is almost certainly an error.
834 including of course general barriers. A write barrier pairs with a data
895 STORE A = 1
903 that the rest of the system might perceive as the unordered set of { STORE A,
911 | | : | A=1 | } \/ the rest of the system
934 STORE A = 1
948 | CPU 1 | : | A=1 | \ --->| C->&Y | V
980 STORE A = 1
994 | CPU 1 | : | A=1 | \ --->| C->&Y |
1020 { A = 0, B = 9 }
1021 STORE A=1
1025 LOAD A
1032 | |------>| A=1 |------ --->| A->0 |
1041 | | A->0 |------>| |
1046 ---->| A->1 |
1052 load of A on CPU 2:
1056 { A = 0, B = 9 }
1057 STORE A=1
1062 LOAD A
1069 | |------>| A=1 |------ --->| A->0 |
1082 prior to the storage of B ---->| A->1 |------>| |
1088 contained a load of A either side of the read barrier:
1092 { A = 0, B = 9 }
1093 STORE A=1
1097 LOAD A [first load of A]
1099 LOAD A [second load of A]
1101 Even though the two loads of A both occur after the load of B, they may both
1106 | |------>| A=1 |------ --->| A->0 |
1118 | | A->0 |------>| 1st |
1122 prior to the storage of B ---->| A->1 |------>| 2nd |
1127 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1132 | |------>| A=1 |------ --->| A->0 |
1144 ---->| A->1 |------>| 1st |
1148 | A->1 |------>| 2nd |
1153 The guarantee is that the second load will always come up with A == 1 if the
1155 A; that may come up with either A == 0 or A == 1.
1179 LOAD A
1189 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1191 LOAD of A : : ~ | |
1208 LOAD A
1220 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1222 LOAD of A : : ~ | |
1242 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1244 LOAD of A : : ~ | |
1250 The speculation is discarded ---> --->| A->1 |------>| |
1277 CPU A follows a load from the same variable executing on CPU B, then
1278 CPU A's load must either return the same value that CPU B's load did,
1651 having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1843 *A = a;
1850 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1863 *A = a;
1870 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1909 *A = a;
1920 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
1922 [+] Note that {*F,*A} indicates a combined access.
1926 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1927 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1928 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1929 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
1961 A general memory barrier is interpolated automatically by set_current_state()
2001 A write memory barrier is implied by wake_up() and co. if and only if they wake
2108 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2115 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2119 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2124 *A, *B or *C following RELEASE M
2442 A driver may be interrupted by its own interrupt service routine, and thus the
2483 A similar situation may occur between an interrupt routine and two routines
2580 A CPU may also discard any instruction sequence that winds up having no
2662 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2667 +--------+ : +--->| Cache A |<------->| |
2686 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2713 <A:modify v=2> v is now in cache A exclusively
2737 <A:modify v=2> <C:busy>
2762 <A:modify v=2> <C:busy>
2816 A memory barrier isn't sufficient in such a case, but rather the cache must be
2825 A programmer might take it for granted that the CPU will perform memory
2829 a = READ_ONCE(*A);
2839 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2871 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2880 U = READ_ONCE(*A);
2881 WRITE_ONCE(*A, V);
2882 WRITE_ONCE(*A, W);
2883 X = READ_ONCE(*A);
2884 WRITE_ONCE(*A, Y);
2885 Z = READ_ONCE(*A);
2890 U == the original value of *A
2893 *A == Y
2898 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2915 *A = V;
2916 *A = W;
2920 *A = W;
2923 assumed that the effect of the storage of V to *A is lost. Similarly:
2925 *A = Y;
2926 Z = *A;
2931 *A = Y;