Lines Matching refs:before

164 into Q before issuing the load of *Q.
345      specified before the barrier will appear to happen before all the STORE
353      memory system as time progresses.  All stores before a write barrier will
366      make sure that the target of the second load is updated before the address
399      LOAD operations specified before the barrier will appear to happen before
416      operations specified before the barrier will appear to happen before all
436      Memory operations that occur before an ACQUIRE operation may appear to
446      memory operations before the RELEASE operation will appear to happen
447      before the RELEASE operation with respect to the other components of the
452      happen before it completes.
484  (*) There is no guarantee that any of the memory accesses specified before a
608 the load from b as having happened before the load from a.  In such a
787 that is, just before or just after the "if" statements.  Furthermore,
874 [!] Note that the stores before the write barrier would normally be expected to
904 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
917 	|       |  :    | E=5  |     }        barrier to be committed before
1128 before the read barrier completes anyway:
1199 Placing a read barrier or a data dependency barrier just before the second
1647 the value of b before loading a[b]), however there is no guarantee in
1649 (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1698      *before* the reference counter is decremented.
1735 		/* flush modifications before status update */
1741 		/* force memory to sync before notifying device via MMIO */
1749      before we read the data from the descriptor, and the dma_wmb() allows
1750      us to guarantee the data is written to the descriptor before the device
1752      cache coherent memory writes have completed before attempting a write to
1803      Memory operations issued before the ACQUIRE may be completed after
1811      Memory operations issued before the RELEASE will be completed before the
1814      Memory operations issued after the RELEASE may be completed before the
1819      All ACQUIRE operations issued before another ACQUIRE operation will be
1820      completed before that ACQUIRE operation.
1824      All ACQUIRE operations issued before a RELEASE operation will be
1825      completed before the RELEASE operation.
1840 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
2002 something up.  The barrier occurs before the task state is cleared, and so sits
2048 order multiple stores before the wake-up with respect to loads of those stored
2159 What is necessary here is to intervene with an mmiowb() before dropping the
2176 before either of the stores issued on CPU 2.
2180 for the mmiowb(), because the load forces the store to complete before the load
2268 before proceeding.  Since the record is on the waiter's stack, this means that
2271 stack before the up*() function has a chance to read the next pointer.
2305 In this case, the barrier makes a guarantee that all memory accesses before the
2306 barrier will appear to happen before all the memory accesses after the barrier
2308 the memory accesses before the barrier will be complete by the time the barrier
2572 earlier instruction must be sufficiently complete[*] before the later
2711 	smp_wmb();			Make sure change to v is visible before
2744 			<C:read *q>	Reads from v before v updated in cache
2755 queue before processing any further requests:
2836 instruction before moving on to the next one, leading to a definite sequence of
2910 The compiler may also combine, discard or defer elements of the sequence before