Lines Matching refs:effects
39 (*) Inter-CPU locking barrier effects.
51 (*) Kernel I/O barrier effects.
55 (*) The effects of the cpu cache.
108 So in the above diagram, the effects of the memory operations performed by a
378 time the barrier completes, the effects of all the stores prior to that
491 indirect effect will be the order in which the second CPU sees the effects
494 (*) There is no guarantee that a CPU will see the correct order of effects
501 mechanisms should propagate the indirect effects of a memory barrier
629 possible highly counterintuitive effects on ordering.
1008 Makes sure all effects ---> \ ddddddddddddddddd | |
1081 barrier causes all effects \ +-------+ | |
1121 barrier causes all effects \ +-------+ | |
1339 The barrier() function has the following effects:
1663 Mandatory barriers should not be used to control SMP effects, since mandatory
1665 used to control MMIO effects on accesses through relaxed memory I/O windows.
1766 ordered I/O regions to be partially ordered. Its effects may go beyond the
1835 one-way barriers is that the effects of instructions outside of a critical
1904 See also the section on "Inter-CPU locking barrier effects".
2351 such the implicit memory barrier effects are necessary.
2578 instructions may depend on different effects.
2629 cacheline over to the accessing CPU and propagate the effects upon conflict.
2640 the order in which the effects are perceived to happen by the other observers