Lines Matching refs:guaranteed

457      pair is -not- guaranteed to act as a full memory barrier.  However, after
459      RELEASE on that same variable are guaranteed to be visible.  In other
461      previous critical sections for that variable are guaranteed to have
469 between two CPUs or between a CPU and a device.  If it can be guaranteed that
686 ordering is guaranteed only when the stores differ, for example:
774 if control dependencies guaranteed transitivity (which they do not),
1286 However, transitivity is -not- guaranteed for read or write barriers.
1676      barrier after it, depending on the function.  It isn't guaranteed to
2025 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2512      They are guaranteed to be fully ordered with respect to each other.
2514      They are not guaranteed to be fully ordered with respect to other types of
2519      Whether these are guaranteed to be fully ordered and uncombined with
2525      Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2550      the same peripheral are guaranteed to be ordered with respect to each
2876 However, it is guaranteed that a CPU will be self-consistent: it will see its