Lines Matching refs:issued

194  (*) On any given CPU, dependent memory accesses will be issued in order, with
237  (*) It _must_not_ be assumed that independent loads and stores will be issued
375      considered can then perceive.  A data dependency barrier issued by the CPU
379      touched by the load will be perceptible to any loads issued after the data
942 effectively random order, despite the write barrier issued by CPU 1:
1028 some effectively random order, despite the write barrier issued by CPU 1:
1800      Memory operations issued after the ACQUIRE will be completed after the
1803      Memory operations issued before the ACQUIRE may be completed after
1811      Memory operations issued before the RELEASE will be completed before the
1814      Memory operations issued after the RELEASE may be completed before the
1819      All ACQUIRE operations issued before another ACQUIRE operation will be
1824      All ACQUIRE operations issued before a RELEASE operation will be
2175 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2176 before either of the stores issued on CPU 2.
2430      issued prior to unlocking the critical section.
2626 CPU that issued it since it may have been satisfied within the CPU's own cache,