85 static uint64_t arc_pmu_read_counter(int idx)  in arc_pmu_read_counter()  argument
94 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_read_counter()
104 				  struct hw_perf_event *hwc, int idx)  in arc_perf_event_update()  argument
107 	uint64_t new_raw_count = arc_pmu_read_counter(idx);  in arc_perf_event_update()
121 	arc_perf_event_update(event, &event->hw, event->hw.idx);  in arc_pmu_read()
219 	int idx = hwc->idx;  in arc_pmu_event_set_period()  local
244 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_event_set_period()
263 	int idx = hwc->idx;  in arc_pmu_start()  local
265 	if (WARN_ON_ONCE(idx == -1))  in arc_pmu_start()
278 			      read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));  in arc_pmu_start()
281 	write_aux_reg(ARC_REG_PCT_INDEX, idx);		/* counter # */  in arc_pmu_start()
288 	int idx = hwc->idx;  in arc_pmu_stop()  local
296 		write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);  in arc_pmu_stop()
298 			      read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~(1 << idx));  in arc_pmu_stop()
303 		write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_stop()
313 		arc_perf_event_update(event, &event->hw, idx);  in arc_pmu_stop()
323 	__clear_bit(event->hw.idx, pmu_cpu->used_mask);  in arc_pmu_del()
325 	pmu_cpu->act_counter[event->hw.idx] = 0;  in arc_pmu_del()
335 	int idx = hwc->idx;  in arc_pmu_add()  local
337 	if (__test_and_set_bit(idx, pmu_cpu->used_mask)) {  in arc_pmu_add()
338 		idx = find_first_zero_bit(pmu_cpu->used_mask,  in arc_pmu_add()
340 		if (idx == arc_pmu->n_counters)  in arc_pmu_add()
343 		__set_bit(idx, pmu_cpu->used_mask);  in arc_pmu_add()
344 		hwc->idx = idx;  in arc_pmu_add()
347 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_add()
349 	pmu_cpu->act_counter[idx] = event;  in arc_pmu_add()
379 	int idx;  in arc_pmu_intr()  local
387 	for (idx = 0; idx < arc_pmu->n_counters; idx++) {  in arc_pmu_intr()
388 		struct perf_event *event = pmu_cpu->act_counter[idx];  in arc_pmu_intr()
391 		if (!(active_ints & (1 << idx)))  in arc_pmu_intr()
395 		write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);  in arc_pmu_intr()
403 			read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));  in arc_pmu_intr()
407 		WARN_ON_ONCE(hwc->idx != idx);  in arc_pmu_intr()
409 		arc_perf_event_update(event, &event->hw, event->hw.idx);  in arc_pmu_intr()