Lines Matching refs:PIN_INPUT_PULLDOWN
173 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
174 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
175 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
181 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
182 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
252 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
258 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
259 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
260 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
261 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
262 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
269 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
270 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
271 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
272 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
273 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
274 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
275 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
276 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
277 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
278 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
279 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
280 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
295 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
296 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
360 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
361 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
363 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
369 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
370 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
371 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
372 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
379 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */