70 static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)  in wakeupgen_writel()  argument
72 	writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +  in wakeupgen_writel()
76 static inline void sar_writel(u32 val, u32 offset, u8 idx)  in sar_writel()  argument
78 	writel_relaxed(val, sar_base + offset + (idx * 4));  in sar_writel()
95 	u32 val, bit_number;  in _wakeupgen_clear()  local
101 	val = wakeupgen_readl(i, cpu);  in _wakeupgen_clear()
102 	val &= ~BIT(bit_number);  in _wakeupgen_clear()
103 	wakeupgen_writel(val, i, cpu);  in _wakeupgen_clear()
108 	u32 val, bit_number;  in _wakeupgen_set()  local
114 	val = wakeupgen_readl(i, cpu);  in _wakeupgen_set()
115 	val |= BIT(bit_number);  in _wakeupgen_set()
116 	wakeupgen_writel(val, i, cpu);  in _wakeupgen_set()
198 	u32 i, val;  in omap4_irq_save_context()  local
205 		val = wakeupgen_readl(i, 0);  in omap4_irq_save_context()
206 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);  in omap4_irq_save_context()
207 		val = wakeupgen_readl(i, 1);  in omap4_irq_save_context()
208 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);  in omap4_irq_save_context()
222 	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);  in omap4_irq_save_context()
223 	writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);  in omap4_irq_save_context()
224 	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);  in omap4_irq_save_context()
225 	writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);  in omap4_irq_save_context()
228 	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);  in omap4_irq_save_context()
229 	writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);  in omap4_irq_save_context()
230 	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);  in omap4_irq_save_context()
231 	writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);  in omap4_irq_save_context()
234 	val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);  in omap4_irq_save_context()
235 	val |= SAR_BACKUP_STATUS_WAKEUPGEN;  in omap4_irq_save_context()
236 	writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);  in omap4_irq_save_context()
242 	u32 i, val;  in omap5_irq_save_context()  local
246 		val = wakeupgen_readl(i, 0);  in omap5_irq_save_context()
247 		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);  in omap5_irq_save_context()
248 		val = wakeupgen_readl(i, 1);  in omap5_irq_save_context()
249 		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);  in omap5_irq_save_context()
255 	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);  in omap5_irq_save_context()
256 	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);  in omap5_irq_save_context()
257 	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);  in omap5_irq_save_context()
258 	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);  in omap5_irq_save_context()
261 	val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);  in omap5_irq_save_context()
262 	val |= SAR_BACKUP_STATUS_WAKEUPGEN;  in omap5_irq_save_context()
263 	writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);  in omap5_irq_save_context()
291 	u32 val;  in irq_sar_clear()  local
297 	val = readl_relaxed(sar_base + offset);  in irq_sar_clear()
298 	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;  in irq_sar_clear()
299 	writel_relaxed(val, sar_base + offset);  in irq_sar_clear()
467 	u32 val;  in wakeupgen_init()  local
534 		val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);  in wakeupgen_init()
535 		val |= BIT(5);  in wakeupgen_init()
536 		omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);  in wakeupgen_init()