Lines Matching refs:aarch64_insn_register

85 enum aarch64_insn_register {  enum
295 				     enum aarch64_insn_register reg,
302 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
304 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
305 				    enum aarch64_insn_register base,
306 				    enum aarch64_insn_register offset,
309 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
310 				     enum aarch64_insn_register reg2,
311 				     enum aarch64_insn_register base,
315 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
316 				 enum aarch64_insn_register src,
319 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
320 			      enum aarch64_insn_register src,
324 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
328 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
329 					 enum aarch64_insn_register src,
330 					 enum aarch64_insn_register reg,
334 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
335 			   enum aarch64_insn_register src,
338 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
339 			   enum aarch64_insn_register src,
340 			   enum aarch64_insn_register reg,
343 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
344 			   enum aarch64_insn_register src,
345 			   enum aarch64_insn_register reg1,
346 			   enum aarch64_insn_register reg2,
349 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
350 					 enum aarch64_insn_register src,
351 					 enum aarch64_insn_register reg,