Lines Matching refs:str
56 str w5, [x3, #VGIC_V3_CPU_VMCR]
57 str w6, [x3, #VGIC_V3_CPU_MISR]
58 str w7, [x3, #VGIC_V3_CPU_EISR]
59 str w8, [x3, #VGIC_V3_CPU_ELRSR]
94 str x20, [x3, #LR_OFFSET(15)]
95 str x19, [x3, #LR_OFFSET(14)]
96 str x18, [x3, #LR_OFFSET(13)]
97 str x17, [x3, #LR_OFFSET(12)]
98 str x16, [x3, #LR_OFFSET(11)]
99 str x15, [x3, #LR_OFFSET(10)]
100 str x14, [x3, #LR_OFFSET(9)]
101 str x13, [x3, #LR_OFFSET(8)]
102 str x12, [x3, #LR_OFFSET(7)]
103 str x11, [x3, #LR_OFFSET(6)]
104 str x10, [x3, #LR_OFFSET(5)]
105 str x9, [x3, #LR_OFFSET(4)]
106 str x8, [x3, #LR_OFFSET(3)]
107 str x7, [x3, #LR_OFFSET(2)]
108 str x6, [x3, #LR_OFFSET(1)]
109 str x5, [x3, #LR_OFFSET(0)]
115 str w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
117 str w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
119 str w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
121 str w17, [x3, #VGIC_V3_CPU_AP0R]
127 str w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
129 str w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
131 str w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
133 str w17, [x3, #VGIC_V3_CPU_AP1R]