267 	unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;  in alchemy_clk_setup_sysbus()  local
271 				      pn, 0, 1, v);  in alchemy_clk_setup_sysbus()
296 	unsigned long v;  in alchemy_clk_setup_mem()  local
303 		v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);  in alchemy_clk_setup_mem()
304 		div = (v & (1 << 15)) ? 1 : 2;  in alchemy_clk_setup_mem()
307 		v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);  in alchemy_clk_setup_mem()
308 		div = (v & (1 << 31)) ? 1 : 2;  in alchemy_clk_setup_mem()
337 	unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);  in alchemy_clk_setup_lrclk()  local
342 		v = 4 + ((v >> 11) & 1);  in alchemy_clk_setup_lrclk()
345 		v = ((v >> 13) & 7) + 1;  in alchemy_clk_setup_lrclk()
348 				      pn, 0, 1, v);  in alchemy_clk_setup_lrclk()
486 	unsigned long v, flags;  in alchemy_clk_fgv1_en()  local
489 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_en()
490 	v |= (1 << 1) << c->shift;  in alchemy_clk_fgv1_en()
491 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_en()
500 	unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);  in alchemy_clk_fgv1_isen()  local
502 	return v & 1;  in alchemy_clk_fgv1_isen()
508 	unsigned long v, flags;  in alchemy_clk_fgv1_dis()  local
511 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_dis()
512 	v &= ~((1 << 1) << c->shift);  in alchemy_clk_fgv1_dis()
513 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_dis()
520 	unsigned long v, flags;  in alchemy_clk_fgv1_setp()  local
523 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_setp()
525 		v |= (1 << c->shift);  in alchemy_clk_fgv1_setp()
527 		v &= ~(1 << c->shift);  in alchemy_clk_fgv1_setp()
528 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_setp()
545 	unsigned long div, v, flags, ret;  in alchemy_clk_fgv1_setr()  local
552 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_setr()
553 	v &= ~(0xff << sh);  in alchemy_clk_fgv1_setr()
554 	v |= div << sh;  in alchemy_clk_fgv1_setr()
555 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_setr()
565 	unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);  in alchemy_clk_fgv1_recalc()  local
567 	v = ((v & 0xff) + 1) * 2;  in alchemy_clk_fgv1_recalc()
568 	return parent_rate / v;  in alchemy_clk_fgv1_recalc()
591 	unsigned long v = alchemy_rdsys(c->reg);  in __alchemy_clk_fgv2_en()  local
593 	v &= ~(3 << c->shift);  in __alchemy_clk_fgv2_en()
594 	v |= (c->parent & 3) << c->shift;  in __alchemy_clk_fgv2_en()
595 	alchemy_wrsys(v, c->reg);  in __alchemy_clk_fgv2_en()
622 	unsigned long v, flags;  in alchemy_clk_fgv2_dis()  local
625 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_dis()
626 	v &= ~(3 << c->shift);	/* set input mux to "disabled" state */  in alchemy_clk_fgv2_dis()
627 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv2_dis()
649 	unsigned long flags, v;  in alchemy_clk_fgv2_getp()  local
652 	v = c->parent - 1;  in alchemy_clk_fgv2_getp()
654 	return v;  in alchemy_clk_fgv2_getp()
667 	unsigned long div, v, flags, ret;  in alchemy_clk_fgv2_setr()  local
672 	v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */  in alchemy_clk_fgv2_setr()
673 	ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,  in alchemy_clk_fgv2_setr()
674 			       v ? 256 : 512, &div);  in alchemy_clk_fgv2_setr()
677 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_setr()
678 	v &= ~(0xff << sh);  in alchemy_clk_fgv2_setr()
679 	v |= (div & 0xff) << sh;  in alchemy_clk_fgv2_setr()
680 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv2_setr()
691 	unsigned long v, t;  in alchemy_clk_fgv2_recalc()  local
693 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_recalc()
694 	t = parent_rate / (((v >> sh) & 0xff) + 1);  in alchemy_clk_fgv2_recalc()
695 	if ((v & (1 << 30)) == 0)		/* test scale bit */  in alchemy_clk_fgv2_recalc()
747 	unsigned long v;  in alchemy_clk_init_fgens()  local
788 			v = alchemy_rdsys(a->reg);  in alchemy_clk_init_fgens()
789 			a->parent = (v >> a->shift) & 3;  in alchemy_clk_init_fgens()
814 	unsigned long v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_isen()  local
816 	return (((v >> c->shift) >> 2) & 7) != 0;  in alchemy_clk_csrc_isen()
821 	unsigned long v = alchemy_rdsys(c->reg);  in __alchemy_clk_csrc_en()  local
823 	v &= ~((7 << 2) << c->shift);  in __alchemy_clk_csrc_en()
824 	v |= ((c->parent & 7) << 2) << c->shift;  in __alchemy_clk_csrc_en()
825 	alchemy_wrsys(v, c->reg);  in __alchemy_clk_csrc_en()
845 	unsigned long v, flags;  in alchemy_clk_csrc_dis()  local
848 	v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_dis()
849 	v &= ~((3 << 2) << c->shift);	/* mux to "disabled" state */  in alchemy_clk_csrc_dis()
850 	alchemy_wrsys(v, c->reg);  in alchemy_clk_csrc_dis()
880 	unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;  in alchemy_clk_csrc_recalc()  local
882 	return parent_rate / c->dt[v];  in alchemy_clk_csrc_recalc()
889 	unsigned long d, v, flags;  in alchemy_clk_csrc_setr()  local
909 	v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_setr()
910 	v &= ~(3 << c->shift);  in alchemy_clk_csrc_setr()
911 	v |= (i & 3) << c->shift;  in alchemy_clk_csrc_setr()
912 	alchemy_wrsys(v, c->reg);  in alchemy_clk_csrc_setr()
953 	unsigned long v;  in alchemy_clk_setup_imux()  local
1007 		v = alchemy_rdsys(a->reg);  in alchemy_clk_setup_imux()
1008 		a->parent = ((v >> a->shift) >> 2) & 7;  in alchemy_clk_setup_imux()