61 	u32 pll;  in ar71xx_clocks_init()  local
67 	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);  in ar71xx_clocks_init()
69 	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;  in ar71xx_clocks_init()
72 	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;  in ar71xx_clocks_init()
75 	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;  in ar71xx_clocks_init()
78 	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;  in ar71xx_clocks_init()
96 	u32 pll;  in ar724x_clocks_init()  local
101 	pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);  in ar724x_clocks_init()
103 	div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);  in ar724x_clocks_init()
106 	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);  in ar724x_clocks_init()
111 	div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;  in ar724x_clocks_init()
114 	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;  in ar724x_clocks_init()
132 	u32 pll;  in ar913x_clocks_init()  local
137 	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);  in ar913x_clocks_init()
139 	div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);  in ar913x_clocks_init()
144 	div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;  in ar913x_clocks_init()
147 	div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;  in ar913x_clocks_init()
247 	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;  in ar934x_clocks_init()  local
260 	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);  in ar934x_clocks_init()
261 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {  in ar934x_clocks_init()
262 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &  in ar934x_clocks_init()
264 		pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);  in ar934x_clocks_init()
265 		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &  in ar934x_clocks_init()
267 		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;  in ar934x_clocks_init()
268 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &  in ar934x_clocks_init()
272 		pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);  in ar934x_clocks_init()
273 		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &  in ar934x_clocks_init()
275 		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in ar934x_clocks_init()
277 		nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &  in ar934x_clocks_init()
279 		nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &  in ar934x_clocks_init()
287 	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);  in ar934x_clocks_init()
288 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {  in ar934x_clocks_init()
289 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &  in ar934x_clocks_init()
291 		pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);  in ar934x_clocks_init()
292 		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &  in ar934x_clocks_init()
294 		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;  in ar934x_clocks_init()
295 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &  in ar934x_clocks_init()
299 		pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);  in ar934x_clocks_init()
300 		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &  in ar934x_clocks_init()
302 		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in ar934x_clocks_init()
304 		nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &  in ar934x_clocks_init()
306 		nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &  in ar934x_clocks_init()
363 	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;  in qca955x_clocks_init()  local
373 	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);  in qca955x_clocks_init()
374 	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &  in qca955x_clocks_init()
376 	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in qca955x_clocks_init()
378 	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &  in qca955x_clocks_init()
380 	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &  in qca955x_clocks_init()
387 	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);  in qca955x_clocks_init()
388 	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &  in qca955x_clocks_init()
390 	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in qca955x_clocks_init()
392 	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &  in qca955x_clocks_init()
394 	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &  in qca955x_clocks_init()