Lines Matching refs:PNX833X_REG

28 #define PNX833X_REG(offs)	(*((volatile unsigned long *)(PNX833X_BASE + offs)))  macro
63 #define PNX833X_CONFIG_MODULE_ID		PNX833X_REG(0x7FFC)
75 #define PNX833X_RESET_CONTROL		PNX833X_REG(0x8004)
76 #define PNX833X_RESET_CONTROL_2		PNX833X_REG(0x8014)
78 #define PNX833X_PIC_REG(offs)		PNX833X_REG(0x01000 + (offs))
85 #define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
90 #define PNX8335_CLOCK_PLL_CPU_CTL		PNX833X_REG(0x9020)
94 #define PNX833X_CONFIG_MUX		PNX833X_REG(0x7004)
97 #define PNX8330_CONFIG_POLYFUSE_7	PNX833X_REG(0x7040)
101 #define PNX833X_PIO_IN		PNX833X_REG(0xF000)
102 #define PNX833X_PIO_OUT		PNX833X_REG(0xF004)
103 #define PNX833X_PIO_DIR		PNX833X_REG(0xF008)
104 #define PNX833X_PIO_SEL		PNX833X_REG(0xF014)
105 #define PNX833X_PIO_INT_EDGE	PNX833X_REG(0xF020)
106 #define PNX833X_PIO_INT_HI	PNX833X_REG(0xF024)
107 #define PNX833X_PIO_INT_LO	PNX833X_REG(0xF028)
108 #define PNX833X_PIO_INT_STATUS	PNX833X_REG(0xFFE0)
109 #define PNX833X_PIO_INT_ENABLE	PNX833X_REG(0xFFE4)
110 #define PNX833X_PIO_INT_CLEAR	PNX833X_REG(0xFFE8)
111 #define PNX833X_PIO_IN2		PNX833X_REG(0xF05C)
112 #define PNX833X_PIO_OUT2	PNX833X_REG(0xF060)
113 #define PNX833X_PIO_DIR2	PNX833X_REG(0xF064)
114 #define PNX833X_PIO_SEL2	PNX833X_REG(0xF068)
124 #define PNX833X_CONFIG_USB		PNX833X_REG(0x7008)
133 #define PNX833X_IDE_MODULE_ID		PNX833X_REG(0x1AFFC)
140 #define PNX833X_MIU_SEL0			PNX833X_REG(0x2004)
141 #define PNX833X_MIU_SEL0_TIMING		PNX833X_REG(0x2008)
142 #define PNX833X_MIU_SEL1			PNX833X_REG(0x200C)
143 #define PNX833X_MIU_SEL1_TIMING		PNX833X_REG(0x2010)
144 #define PNX833X_MIU_SEL2			PNX833X_REG(0x2014)
145 #define PNX833X_MIU_SEL2_TIMING		PNX833X_REG(0x2018)
146 #define PNX833X_MIU_SEL3			PNX833X_REG(0x201C)
147 #define PNX833X_MIU_SEL3_TIMING		PNX833X_REG(0x2020)
158 #define PNX833X_MIU_CONFIG_SPI		PNX833X_REG(0x2000)
181 #define PNX8335_IP3902_MODULE_ID		PNX833X_REG(0x2FFFC)
196 #define PNX8335_SATA_MODULE_ID		PNX833X_REG(0x2EFFC)