Lines Matching refs:_ULCAST_
36 #define _ULCAST_ macro
38 #define _ULCAST_ (unsigned long) macro
122 #define ENTRYLO_G (_ULCAST_(1) << 0)
123 #define ENTRYLO_V (_ULCAST_(1) << 1)
124 #define ENTRYLO_D (_ULCAST_(1) << 2)
126 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
129 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
130 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
131 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
132 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
136 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
137 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
224 #define PG_RIE (_ULCAST_(1) << 31)
225 #define PG_XIE (_ULCAST_(1) << 30)
226 #define PG_ELPA (_ULCAST_(1) << 29)
227 #define PG_ESP (_ULCAST_(1) << 28)
228 #define PG_IEC (_ULCAST_(1) << 27)
231 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
236 #define IE_SW0 (_ULCAST_(1) << 8)
237 #define IE_SW1 (_ULCAST_(1) << 9)
238 #define IE_IRQ0 (_ULCAST_(1) << 10)
239 #define IE_IRQ1 (_ULCAST_(1) << 11)
240 #define IE_IRQ2 (_ULCAST_(1) << 12)
241 #define IE_IRQ3 (_ULCAST_(1) << 13)
242 #define IE_IRQ4 (_ULCAST_(1) << 14)
243 #define IE_IRQ5 (_ULCAST_(1) << 15)
248 #define C_SW0 (_ULCAST_(1) << 8)
249 #define C_SW1 (_ULCAST_(1) << 9)
250 #define C_IRQ0 (_ULCAST_(1) << 10)
251 #define C_IRQ1 (_ULCAST_(1) << 11)
252 #define C_IRQ2 (_ULCAST_(1) << 12)
253 #define C_IRQ3 (_ULCAST_(1) << 13)
254 #define C_IRQ4 (_ULCAST_(1) << 14)
255 #define C_IRQ5 (_ULCAST_(1) << 15)
297 #define ST0_UM (_ULCAST_(1) << 4)
298 #define ST0_IL (_ULCAST_(1) << 23)
299 #define ST0_DL (_ULCAST_(1) << 24)
311 #define STATUSF_IP0 (_ULCAST_(1) << 8)
313 #define STATUSF_IP1 (_ULCAST_(1) << 9)
315 #define STATUSF_IP2 (_ULCAST_(1) << 10)
317 #define STATUSF_IP3 (_ULCAST_(1) << 11)
319 #define STATUSF_IP4 (_ULCAST_(1) << 12)
321 #define STATUSF_IP5 (_ULCAST_(1) << 13)
323 #define STATUSF_IP6 (_ULCAST_(1) << 14)
325 #define STATUSF_IP7 (_ULCAST_(1) << 15)
327 #define STATUSF_IP8 (_ULCAST_(1) << 0)
329 #define STATUSF_IP9 (_ULCAST_(1) << 1)
331 #define STATUSF_IP10 (_ULCAST_(1) << 2)
333 #define STATUSF_IP11 (_ULCAST_(1) << 3)
335 #define STATUSF_IP12 (_ULCAST_(1) << 4)
337 #define STATUSF_IP13 (_ULCAST_(1) << 5)
339 #define STATUSF_IP14 (_ULCAST_(1) << 6)
341 #define STATUSF_IP15 (_ULCAST_(1) << 7)
360 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
362 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
364 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
372 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
374 #define CAUSEF_IP (_ULCAST_(255) << 8)
376 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
378 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
380 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
382 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
384 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
386 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
388 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
390 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
392 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
394 #define CAUSEF_IV (_ULCAST_(1) << 23)
396 #define CAUSEF_PCI (_ULCAST_(1) << 26)
398 #define CAUSEF_CE (_ULCAST_(3) << 28)
400 #define CAUSEF_TI (_ULCAST_(1) << 30)
402 #define CAUSEF_BD (_ULCAST_(1) << 31)
417 #define CONF_BE (_ULCAST_(1) << 15)
420 #define CONF_CU (_ULCAST_(1) << 3)
421 #define CONF_DB (_ULCAST_(1) << 4)
422 #define CONF_IB (_ULCAST_(1) << 5)
423 #define CONF_DC (_ULCAST_(7) << 6)
424 #define CONF_IC (_ULCAST_(7) << 9)
425 #define CONF_EB (_ULCAST_(1) << 13)
426 #define CONF_EM (_ULCAST_(1) << 14)
427 #define CONF_SM (_ULCAST_(1) << 16)
428 #define CONF_SC (_ULCAST_(1) << 17)
429 #define CONF_EW (_ULCAST_(3) << 18)
430 #define CONF_EP (_ULCAST_(15)<< 24)
431 #define CONF_EC (_ULCAST_(7) << 28)
432 #define CONF_CM (_ULCAST_(1) << 31)
435 #define R4K_CONF_SW (_ULCAST_(1) << 20)
436 #define R4K_CONF_SS (_ULCAST_(1) << 21)
437 #define R4K_CONF_SB (_ULCAST_(3) << 22)
440 #define R5K_CONF_SE (_ULCAST_(1) << 12)
441 #define R5K_CONF_SS (_ULCAST_(3) << 20)
444 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
445 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
446 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
447 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
448 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
449 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
452 #define R10K_CONF_DN (_ULCAST_(3) << 3)
453 #define R10K_CONF_CT (_ULCAST_(1) << 5)
454 #define R10K_CONF_PE (_ULCAST_(1) << 6)
455 #define R10K_CONF_PM (_ULCAST_(3) << 7)
456 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
457 #define R10K_CONF_SB (_ULCAST_(1) << 13)
458 #define R10K_CONF_SK (_ULCAST_(1) << 14)
459 #define R10K_CONF_SS (_ULCAST_(7) << 16)
460 #define R10K_CONF_SC (_ULCAST_(7) << 19)
461 #define R10K_CONF_DC (_ULCAST_(7) << 26)
462 #define R10K_CONF_IC (_ULCAST_(7) << 29)
465 #define VR41_CONF_CS (_ULCAST_(1) << 12)
466 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
467 #define VR41_CONF_BP (_ULCAST_(1) << 16)
468 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
469 #define VR41_CONF_AD (_ULCAST_(1) << 23)
472 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
473 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
474 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
475 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
476 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
477 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
478 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
479 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
480 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
483 #define TX49_CONF_DC (_ULCAST_(1) << 16)
484 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
485 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
486 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
489 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
490 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
491 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
492 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
493 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
494 #define MIPS_CONF_M (_ULCAST_(1) << 31)
499 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
500 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
501 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
502 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
503 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
504 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
505 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
508 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
511 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
514 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
517 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
520 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
523 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
526 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
528 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
529 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
530 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
531 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
532 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
533 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
534 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
535 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
537 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
538 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
539 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
540 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
541 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
542 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
543 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
544 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
545 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
546 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
547 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
548 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
549 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
550 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
551 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
552 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
553 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
554 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
555 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
556 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
557 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
558 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
559 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
560 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
561 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
562 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
563 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
566 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
568 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
570 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
573 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
575 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
576 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
577 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
578 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
579 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
580 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
582 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
583 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
584 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
585 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
587 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
588 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
589 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
590 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
591 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
592 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
593 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
594 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
595 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
596 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
597 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
599 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
601 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
605 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
607 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
609 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
610 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
617 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
618 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
622 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
628 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
630 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
632 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
634 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
636 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
637 #define MIPS_SEGCFG_USK _ULCAST_(5)
638 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
639 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
640 #define MIPS_SEGCFG_MSK _ULCAST_(2)
641 #define MIPS_SEGCFG_MK _ULCAST_(1)
642 #define MIPS_SEGCFG_UK _ULCAST_(0)
677 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
678 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
679 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
720 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
722 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
724 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
741 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
742 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
743 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
744 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
745 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
746 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
747 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
748 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
749 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
750 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
756 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
758 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
760 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
762 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
764 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
766 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
768 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
770 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
772 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
778 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
784 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
787 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
790 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
792 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
794 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
796 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
798 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
800 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
802 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
804 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
810 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
812 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
813 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1942 if ((res & _ULCAST_(1))) in tlb_read()