Lines Matching refs:CNTR_ALL
66 #define CNTR_ALL 0xffffffff macro
836 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
837 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
838 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
839 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
840 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
841 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
842 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
853 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
854 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
855 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
856 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
857 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
858 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
1139 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1140 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1143 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1148 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1151 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1160 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1163 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1168 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1179 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1180 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1183 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1184 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1189 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1190 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1195 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1196 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1199 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1200 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1209 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1212 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1217 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1220 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1225 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },
1625 raw_event.cntr_mask = CNTR_ALL; in octeon_pmu_map_raw_event()
1660 raw_event.cntr_mask = CNTR_ALL; in xlp_pmu_map_raw_event()