64 	#define CNTR_EVEN	0x55555555  macro
813 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
814 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
815 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
822 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
823 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
824 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
829 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
831 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
847 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
848 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
874 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
875 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
878 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
879 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
884 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
888 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
892 		[C(RESULT_ACCESS)]	= { 0x14, CNTR_EVEN, T },
902 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
906 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
911 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
915 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
921 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
925 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
932 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
936 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
965 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
969 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
973 		[C(RESULT_ACCESS)]	= { 0x34, CNTR_EVEN, T },
983 		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },
987 		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },
997 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1001 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1008 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1012 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1038 		[C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1041 		[C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1063 		[C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN },
1067 		[C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN },
1086 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1090 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1096 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1100 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1104 		[C(RESULT_ACCESS)]	= { 23, CNTR_EVEN, T },
1113 		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
1117 		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
1510 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1513 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1524 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1527 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1540 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1543 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1550 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1553 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1564 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1567 				raw_id > 255 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1574 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1577 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1589 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1592 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1604 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1607 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1610 		raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()