65 	#define CNTR_ODD	0xaaaaaaaa  macro
813 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
814 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
816 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
822 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
823 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
825 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
830 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
832 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
847 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
848 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
849 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
875 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
879 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
885 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
889 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
901 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
905 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
912 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
916 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
922 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
926 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
933 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
937 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
955 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
956 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
959 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
960 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
966 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
970 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
982 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
986 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
998 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1002 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1009 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1013 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1030 		[C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
1033 		[C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
1046 		[C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
1049 		[C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
1054 		[C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
1057 		[C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
1064 		[C(RESULT_MISS)]        = { 0x02, CNTR_ODD },
1068 		[C(RESULT_MISS)]        = { 0x02, CNTR_ODD },
1087 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1091 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1097 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1101 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1114 		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
1118 		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
1124 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1127 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1510 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1513 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1524 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1527 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1540 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1543 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1550 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1553 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1564 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1567 				raw_id > 255 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1574 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1577 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1589 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1592 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1604 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1607 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1610 		raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()