102 static struct mips_pmu mipspmu;  variable
322 	for (i = mipspmu.num_counters - 1; i >= 0; i--) {  in mipsxx_pmu_alloc_counter()
345 	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);  in mipsxx_pmu_enable_event()
366 	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);  in mipsxx_pmu_disable_event()
397 	if (left > mipspmu.max_period) {  in mipspmu_event_set_period()
398 		left = mipspmu.max_period;  in mipspmu_event_set_period()
402 	local64_set(&hwc->prev_count, mipspmu.overflow - left);  in mipspmu_event_set_period()
404 	mipspmu.write_counter(idx, mipspmu.overflow - left);  in mipspmu_event_set_period()
420 	new_raw_count = mipspmu.read_counter(idx);  in mipspmu_event_update()
503 	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);  in mipspmu_del()
558 	if (mipspmu.irq >= 0) {  in mipspmu_get_irq()
560 		err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,  in mipspmu_get_irq()
564 				  "mips_perf_pmu", &mipspmu);  in mipspmu_get_irq()
567 				mipspmu.irq);  in mipspmu_get_irq()
586 	if (mipspmu.irq >= 0)  in mipspmu_free_irq()
587 		free_irq(mipspmu.irq, &mipspmu);  in mipspmu_free_irq()
608 			(void *)(long)mipspmu.num_counters, 1);  in hw_perf_event_destroy()
682 	if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)  in mipspmu_map_general_event()
684 	return &(*mipspmu.general_event_map)[idx];  in mipspmu_map_general_event()
704 	pev = &((*mipspmu.cache_event_map)  in mipspmu_map_cache_event()
797 		mipspmu.write_counter(3, 0);  in reset_counters()
800 		mipspmu.write_counter(2, 0);  in reset_counters()
803 		mipspmu.write_counter(1, 0);  in reset_counters()
806 		mipspmu.write_counter(0, 0);  in reset_counters()
1278 		pev = mipspmu.map_raw_event(event->attr.config);  in __hw_perf_event_init()
1323 		hwc->sample_period  = mipspmu.max_period;  in __hw_perf_event_init()
1343 	int ctr = mipspmu.num_counters;  in pause_local_counters()
1359 	int ctr = mipspmu.num_counters;  in resume_local_counters()
1371 	unsigned int counters = mipspmu.num_counters;  in mipsxx_pmu_handle_shared_irq()
1398 			counter = mipspmu.read_counter(n);		\  in mipsxx_pmu_handle_shared_irq()
1399 			if (counter & mipspmu.overflow) {		\  in mipsxx_pmu_handle_shared_irq()
1693 	mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;  in init_hw_perf_events()
1697 		mipspmu.name = "mips/24K";  in init_hw_perf_events()
1698 		mipspmu.general_event_map = &mipsxxcore_event_map;  in init_hw_perf_events()
1699 		mipspmu.cache_event_map = &mipsxxcore_cache_map;  in init_hw_perf_events()
1702 		mipspmu.name = "mips/34K";  in init_hw_perf_events()
1703 		mipspmu.general_event_map = &mipsxxcore_event_map;  in init_hw_perf_events()
1704 		mipspmu.cache_event_map = &mipsxxcore_cache_map;  in init_hw_perf_events()
1707 		mipspmu.name = "mips/74K";  in init_hw_perf_events()
1708 		mipspmu.general_event_map = &mipsxxcore_event_map2;  in init_hw_perf_events()
1709 		mipspmu.cache_event_map = &mipsxxcore_cache_map2;  in init_hw_perf_events()
1712 		mipspmu.name = "mips/proAptiv";  in init_hw_perf_events()
1713 		mipspmu.general_event_map = &mipsxxcore_event_map2;  in init_hw_perf_events()
1714 		mipspmu.cache_event_map = &mipsxxcore_cache_map2;  in init_hw_perf_events()
1717 		mipspmu.name = "mips/P5600";  in init_hw_perf_events()
1718 		mipspmu.general_event_map = &mipsxxcore_event_map2;  in init_hw_perf_events()
1719 		mipspmu.cache_event_map = &mipsxxcore_cache_map2;  in init_hw_perf_events()
1722 		mipspmu.name = "mips/I6400";  in init_hw_perf_events()
1723 		mipspmu.general_event_map = &mipsxxcore_event_map2;  in init_hw_perf_events()
1724 		mipspmu.cache_event_map = &mipsxxcore_cache_map2;  in init_hw_perf_events()
1727 		mipspmu.name = "mips/1004K";  in init_hw_perf_events()
1728 		mipspmu.general_event_map = &mipsxxcore_event_map;  in init_hw_perf_events()
1729 		mipspmu.cache_event_map = &mipsxxcore_cache_map;  in init_hw_perf_events()
1732 		mipspmu.name = "mips/1074K";  in init_hw_perf_events()
1733 		mipspmu.general_event_map = &mipsxxcore_event_map;  in init_hw_perf_events()
1734 		mipspmu.cache_event_map = &mipsxxcore_cache_map;  in init_hw_perf_events()
1737 		mipspmu.name = "mips/interAptiv";  in init_hw_perf_events()
1738 		mipspmu.general_event_map = &mipsxxcore_event_map;  in init_hw_perf_events()
1739 		mipspmu.cache_event_map = &mipsxxcore_cache_map;  in init_hw_perf_events()
1742 		mipspmu.name = "mips/loongson1";  in init_hw_perf_events()
1743 		mipspmu.general_event_map = &mipsxxcore_event_map;  in init_hw_perf_events()
1744 		mipspmu.cache_event_map = &mipsxxcore_cache_map;  in init_hw_perf_events()
1747 		mipspmu.name = "mips/loongson3";  in init_hw_perf_events()
1748 		mipspmu.general_event_map = &loongson3_event_map;  in init_hw_perf_events()
1749 		mipspmu.cache_event_map = &loongson3_cache_map;  in init_hw_perf_events()
1754 		mipspmu.name = "octeon";  in init_hw_perf_events()
1755 		mipspmu.general_event_map = &octeon_event_map;  in init_hw_perf_events()
1756 		mipspmu.cache_event_map = &octeon_cache_map;  in init_hw_perf_events()
1757 		mipspmu.map_raw_event = octeon_pmu_map_raw_event;  in init_hw_perf_events()
1760 		mipspmu.name = "BMIPS5000";  in init_hw_perf_events()
1761 		mipspmu.general_event_map = &bmips5000_event_map;  in init_hw_perf_events()
1762 		mipspmu.cache_event_map = &bmips5000_cache_map;  in init_hw_perf_events()
1765 		mipspmu.name = "xlp";  in init_hw_perf_events()
1766 		mipspmu.general_event_map = &xlp_event_map;  in init_hw_perf_events()
1767 		mipspmu.cache_event_map = &xlp_cache_map;  in init_hw_perf_events()
1768 		mipspmu.map_raw_event = xlp_pmu_map_raw_event;  in init_hw_perf_events()
1776 	mipspmu.num_counters = counters;  in init_hw_perf_events()
1777 	mipspmu.irq = irq;  in init_hw_perf_events()
1780 		mipspmu.max_period = (1ULL << 63) - 1;  in init_hw_perf_events()
1781 		mipspmu.valid_count = (1ULL << 63) - 1;  in init_hw_perf_events()
1782 		mipspmu.overflow = 1ULL << 63;  in init_hw_perf_events()
1783 		mipspmu.read_counter = mipsxx_pmu_read_counter_64;  in init_hw_perf_events()
1784 		mipspmu.write_counter = mipsxx_pmu_write_counter_64;  in init_hw_perf_events()
1787 		mipspmu.max_period = (1ULL << 31) - 1;  in init_hw_perf_events()
1788 		mipspmu.valid_count = (1ULL << 31) - 1;  in init_hw_perf_events()
1789 		mipspmu.overflow = 1ULL << 31;  in init_hw_perf_events()
1790 		mipspmu.read_counter = mipsxx_pmu_read_counter;  in init_hw_perf_events()
1791 		mipspmu.write_counter = mipsxx_pmu_write_counter;  in init_hw_perf_events()
1798 		"CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,  in init_hw_perf_events()