49 #define SMSC_WRITE_INDEXED(val, index) ({ \  macro
86 	SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);  in smsc_superio_setup()
88 	SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);  in smsc_superio_setup()
90 	SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);  in smsc_superio_setup()
91 	SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);  in smsc_superio_setup()
94 	SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);  in smsc_superio_setup()
96 	SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);  in smsc_superio_setup()
98 	SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);  in smsc_superio_setup()
99 	SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);  in smsc_superio_setup()
100 	SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);  in smsc_superio_setup()
102 	SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);  in smsc_superio_setup()
105 	SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);  in smsc_superio_setup()
107 	SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);  in smsc_superio_setup()
109 	SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);  in smsc_superio_setup()
110 	SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);  in smsc_superio_setup()
111 	SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);  in smsc_superio_setup()
113 	SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);  in smsc_superio_setup()
116 	SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);  in smsc_superio_setup()
118 	SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);  in smsc_superio_setup()
120 	SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);  in smsc_superio_setup()
121 	SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);  in smsc_superio_setup()
122 	SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);  in smsc_superio_setup()
123 	SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);  in smsc_superio_setup()
124 	SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);  in smsc_superio_setup()
125 	SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);  in smsc_superio_setup()
127 	SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);  in smsc_superio_setup()
130 	SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);  in smsc_superio_setup()
132 	SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);  in smsc_superio_setup()
134 	SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);  in smsc_superio_setup()
135 	SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);  in smsc_superio_setup()
136 	SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);  in smsc_superio_setup()
137 	SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);  in smsc_superio_setup()
139 	SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);  in smsc_superio_setup()
142 	SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);  in smsc_superio_setup()
149 	SMSC_WRITE_INDEXED(0x00, 0xc2);	/* GP42 = nIDE1_OE */  in smsc_superio_setup()
150 	SMSC_WRITE_INDEXED(0x01, 0xc5);	/* GP45 = IDE1_IRQ */  in smsc_superio_setup()
151 	SMSC_WRITE_INDEXED(0x00, 0xc6);	/* GP46 = nIOROP */  in smsc_superio_setup()
152 	SMSC_WRITE_INDEXED(0x00, 0xc7);	/* GP47 = nIOWOP */  in smsc_superio_setup()
153 	SMSC_WRITE_INDEXED(0x08, 0xe8);	/* GP20 = nIDE2_OE */  in smsc_superio_setup()