170 	unsigned char dir0, dir0_msn, dir1 = 0;  in early_init_cyrix()  local
173 	dir0_msn = dir0 >> 4; /* identifies CPU "family"   */  in early_init_cyrix()
175 	switch (dir0_msn) {  in early_init_cyrix()
189 	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;  in init_cyrix()  local
209 	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */  in init_cyrix()
222 	switch (dir0_msn) {  in init_cyrix()
315 			dir0_msn++;  /* M II */  in init_cyrix()
334 			dir0_msn = 0;  in init_cyrix()
339 			dir0_msn = 0;  in init_cyrix()
346 		dir0_msn = 7;  in init_cyrix()
349 	strcpy(buf, Cx86_model[dir0_msn & 7]);  in init_cyrix()