Lines Matching refs:x86_pmu
1498 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); in __intel_pmu_enable_all()
1681 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) in intel_pmu_enable_fixed()
1758 if (!x86_pmu.num_counters) in intel_pmu_reset()
1765 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in intel_pmu_reset()
1769 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) in intel_pmu_reset()
1776 if (x86_pmu.version >= 2) { in intel_pmu_reset()
1782 if (x86_pmu.lbr_nr) { in intel_pmu_reset()
1808 if (!x86_pmu.late_ack) in intel_pmu_handle_irq()
1850 x86_pmu.drain_pebs(regs); in intel_pmu_handle_irq()
1860 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; in intel_pmu_handle_irq()
1915 if (x86_pmu.late_ack) in intel_pmu_handle_irq()
1930 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); in intel_bts_constraints()
1941 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) in intel_alt_er()
1950 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) in intel_alt_er()
1962 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; in intel_fixup_er()
1966 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; in intel_fixup_er()
2109 if (x86_pmu.event_constraints) { in x86_get_event_constraints()
2110 for_each_event_constraint(c, x86_pmu.event_constraints) { in x86_get_event_constraints()
2501 unsigned long flags = x86_pmu.free_running_flags; in intel_pmu_free_running_flags()
2522 if (x86_pmu.pebs_aliases) in intel_pmu_hw_config()
2523 x86_pmu.pebs_aliases(event); in intel_pmu_hw_config()
2549 if (x86_pmu.version < 3) in intel_pmu_hw_config()
2562 if (x86_pmu.guest_get_msrs) in perf_guest_get_msrs()
2563 return x86_pmu.guest_get_msrs(nr); in perf_guest_get_msrs()
2575 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; in intel_guest_get_msrs()
2576 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; in intel_guest_get_msrs()
2596 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in core_guest_get_msrs()
2614 *nr = x86_pmu.num_counters; in core_guest_get_msrs()
2629 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in core_pmu_enable_all()
2787 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { in intel_pmu_cpu_prepare()
2793 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { in intel_pmu_cpu_prepare()
2838 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { in intel_pmu_cpu_starting()
2855 if (x86_pmu.lbr_sel_map) in intel_pmu_cpu_starting()
2858 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { in intel_pmu_cpu_starting()
2910 if (x86_pmu.pebs_active) in intel_pmu_sched_task()
2912 if (x86_pmu.lbr_nr) in intel_pmu_sched_task()
2943 static __initconst const struct x86_pmu core_pmu = {
2983 static __initconst const struct x86_pmu intel_pmu = {
3040 x86_pmu.pebs = 0; in intel_clovertown_quirk()
3041 x86_pmu.pebs_constraints = NULL; in intel_clovertown_quirk()
3075 if (pebs_broken == x86_pmu.pebs_broken) in intel_snb_check_microcode()
3081 if (x86_pmu.pebs_broken) { in intel_snb_check_microcode()
3083 x86_pmu.pebs_broken = 0; in intel_snb_check_microcode()
3086 x86_pmu.pebs_broken = 1; in intel_snb_check_microcode()
3127 x86_pmu.check_microcode = intel_snb_check_microcode; in intel_sandybridge_quirk()
3146 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { in intel_arch_events_quirk()
3157 ebx.full = x86_pmu.events_maskl; in intel_nehalem_quirk()
3167 x86_pmu.events_maskl = ebx.full; in intel_nehalem_quirk()
3186 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; in intel_ht_bug()
3188 x86_pmu.start_scheduling = intel_start_scheduling; in intel_ht_bug()
3189 x86_pmu.commit_scheduling = intel_commit_scheduling; in intel_ht_bug()
3190 x86_pmu.stop_scheduling = intel_stop_scheduling; in intel_ht_bug()
3260 x86_pmu = core_pmu; in intel_pmu_init()
3262 x86_pmu = intel_pmu; in intel_pmu_init()
3264 x86_pmu.version = version; in intel_pmu_init()
3265 x86_pmu.num_counters = eax.split.num_counters; in intel_pmu_init()
3266 x86_pmu.cntval_bits = eax.split.bit_width; in intel_pmu_init()
3267 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()
3269 x86_pmu.events_maskl = ebx.full; in intel_pmu_init()
3270 x86_pmu.events_mask_len = eax.split.mask_length; in intel_pmu_init()
3272 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); in intel_pmu_init()
3279 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); in intel_pmu_init()
3285 x86_pmu.intel_cap.capabilities = capabilities; in intel_pmu_init()
3310 x86_pmu.event_constraints = intel_core2_event_constraints; in intel_pmu_init()
3311 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; in intel_pmu_init()
3325 x86_pmu.event_constraints = intel_nehalem_event_constraints; in intel_pmu_init()
3326 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; in intel_pmu_init()
3327 x86_pmu.enable_all = intel_pmu_nhm_enable_all; in intel_pmu_init()
3328 x86_pmu.extra_regs = intel_nehalem_extra_regs; in intel_pmu_init()
3330 x86_pmu.cpu_events = nhm_events_attrs; in intel_pmu_init()
3355 x86_pmu.event_constraints = intel_gen_event_constraints; in intel_pmu_init()
3356 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; in intel_pmu_init()
3370 x86_pmu.event_constraints = intel_slm_event_constraints; in intel_pmu_init()
3371 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; in intel_pmu_init()
3372 x86_pmu.extra_regs = intel_slm_extra_regs; in intel_pmu_init()
3373 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3387 x86_pmu.event_constraints = intel_westmere_event_constraints; in intel_pmu_init()
3388 x86_pmu.enable_all = intel_pmu_nhm_enable_all; in intel_pmu_init()
3389 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; in intel_pmu_init()
3390 x86_pmu.extra_regs = intel_westmere_extra_regs; in intel_pmu_init()
3391 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3393 x86_pmu.cpu_events = nhm_events_attrs; in intel_pmu_init()
3417 x86_pmu.event_constraints = intel_snb_event_constraints; in intel_pmu_init()
3418 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; in intel_pmu_init()
3419 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3421 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
3423 x86_pmu.extra_regs = intel_snb_extra_regs; in intel_pmu_init()
3427 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3428 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3430 x86_pmu.cpu_events = snb_events_attrs; in intel_pmu_init()
3455 x86_pmu.event_constraints = intel_ivb_event_constraints; in intel_pmu_init()
3456 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; in intel_pmu_init()
3457 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3459 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
3461 x86_pmu.extra_regs = intel_snb_extra_regs; in intel_pmu_init()
3463 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3464 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3466 x86_pmu.cpu_events = snb_events_attrs; in intel_pmu_init()
3481 x86_pmu.late_ack = true; in intel_pmu_init()
3487 x86_pmu.event_constraints = intel_hsw_event_constraints; in intel_pmu_init()
3488 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; in intel_pmu_init()
3489 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
3490 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3492 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3493 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3495 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
3496 x86_pmu.get_event_constraints = hsw_get_event_constraints; in intel_pmu_init()
3497 x86_pmu.cpu_events = hsw_events_attrs; in intel_pmu_init()
3498 x86_pmu.lbr_double_abort = true; in intel_pmu_init()
3506 x86_pmu.late_ack = true; in intel_pmu_init()
3522 x86_pmu.event_constraints = intel_bdw_event_constraints; in intel_pmu_init()
3523 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; in intel_pmu_init()
3524 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
3525 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3527 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3528 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3530 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
3531 x86_pmu.get_event_constraints = hsw_get_event_constraints; in intel_pmu_init()
3532 x86_pmu.cpu_events = hsw_events_attrs; in intel_pmu_init()
3533 x86_pmu.limit_period = bdw_limit_period; in intel_pmu_init()
3539 x86_pmu.late_ack = true; in intel_pmu_init()
3544 x86_pmu.event_constraints = intel_skl_event_constraints; in intel_pmu_init()
3545 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; in intel_pmu_init()
3546 x86_pmu.extra_regs = intel_skl_extra_regs; in intel_pmu_init()
3547 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3549 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3550 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3552 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
3553 x86_pmu.get_event_constraints = hsw_get_event_constraints; in intel_pmu_init()
3554 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, in intel_pmu_init()
3556 WARN_ON(!x86_pmu.format_attrs); in intel_pmu_init()
3557 x86_pmu.cpu_events = hsw_events_attrs; in intel_pmu_init()
3562 switch (x86_pmu.version) { in intel_pmu_init()
3564 x86_pmu.event_constraints = intel_v1_event_constraints; in intel_pmu_init()
3571 x86_pmu.event_constraints = intel_gen_event_constraints; in intel_pmu_init()
3577 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { in intel_pmu_init()
3579 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); in intel_pmu_init()
3580 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; in intel_pmu_init()
3582 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; in intel_pmu_init()
3584 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { in intel_pmu_init()
3586 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); in intel_pmu_init()
3587 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; in intel_pmu_init()
3590 x86_pmu.intel_ctrl |= in intel_pmu_init()
3591 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; in intel_pmu_init()
3593 if (x86_pmu.event_constraints) { in intel_pmu_init()
3598 for_each_event_constraint(c, x86_pmu.event_constraints) { in intel_pmu_init()
3601 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; in intel_pmu_init()
3604 ~(~0UL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); in intel_pmu_init()
3615 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) in intel_pmu_init()
3616 x86_pmu.lbr_nr = 0; in intel_pmu_init()
3617 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_init()
3618 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && in intel_pmu_init()
3619 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) in intel_pmu_init()
3620 x86_pmu.lbr_nr = 0; in intel_pmu_init()
3628 if (x86_pmu.extra_regs) { in intel_pmu_init()
3629 for (er = x86_pmu.extra_regs; er->msr; er++) { in intel_pmu_init()
3633 x86_pmu.lbr_sel_map = NULL; in intel_pmu_init()
3638 if (x86_pmu.intel_cap.full_width_write) { in intel_pmu_init()
3639 x86_pmu.max_period = x86_pmu.cntval_mask; in intel_pmu_init()
3640 x86_pmu.perfctr = MSR_IA32_PMC0; in intel_pmu_init()
3660 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) in fixup_ht_bug()
3674 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); in fixup_ht_bug()
3676 x86_pmu.start_scheduling = NULL; in fixup_ht_bug()
3677 x86_pmu.commit_scheduling = NULL; in fixup_ht_bug()
3678 x86_pmu.stop_scheduling = NULL; in fixup_ht_bug()