218 			reg = &arch_cntr_pair[index].counter;  in xen_intel_pmu_emulate()
329 static unsigned long long xen_amd_read_pmc(int counter)  in xen_amd_read_pmc()  argument
340 		msr = amd_counters_base + (counter * amd_msr_step);  in xen_amd_read_pmc()
346 	return counter_regs[counter];  in xen_amd_read_pmc()
349 static unsigned long long xen_intel_read_pmc(int counter)  in xen_intel_read_pmc()  argument
361 		if (counter & (1 << INTEL_PMC_TYPE_SHIFT))  in xen_intel_read_pmc()
362 			msr = MSR_CORE_PERF_FIXED_CTR0 + (counter & 0xffff);  in xen_intel_read_pmc()
364 			msr = MSR_IA32_PERFCTR0 + counter;  in xen_intel_read_pmc()
370 	if (counter & (1 << INTEL_PMC_TYPE_SHIFT)) {  in xen_intel_read_pmc()
372 		return fixed_counters[counter & 0xffff];  in xen_intel_read_pmc()
376 	return arch_cntr_pair[counter].counter;  in xen_intel_read_pmc()
379 unsigned long long xen_read_pmc(int counter)  in xen_read_pmc()  argument
382 		return xen_amd_read_pmc(counter);  in xen_read_pmc()
384 		return xen_intel_read_pmc(counter);  in xen_read_pmc()