129 static inline uint32_t xtensa_pmu_read_counter(int idx)  in xtensa_pmu_read_counter()  argument
131 	return get_er(XTENSA_PMU_PM(idx));  in xtensa_pmu_read_counter()
134 static inline void xtensa_pmu_write_counter(int idx, uint32_t v)  in xtensa_pmu_write_counter()  argument
136 	set_er(v, XTENSA_PMU_PM(idx));  in xtensa_pmu_write_counter()
140 				     struct hw_perf_event *hwc, int idx)  in xtensa_perf_event_update()  argument
147 		new_raw_count = xtensa_pmu_read_counter(event->hw.idx);  in xtensa_perf_event_update()
158 					 struct hw_perf_event *hwc, int idx)  in xtensa_perf_event_set_period()  argument
185 	xtensa_pmu_write_counter(idx, -left);  in xtensa_perf_event_set_period()
246 	int idx = hwc->idx;  in xtensa_pmu_start()  local
248 	if (WARN_ON_ONCE(idx == -1))  in xtensa_pmu_start()
253 		xtensa_perf_event_set_period(event, hwc, idx);  in xtensa_pmu_start()
258 	set_er(hwc->config, XTENSA_PMU_PMCTRL(idx));  in xtensa_pmu_start()
264 	int idx = hwc->idx;  in xtensa_pmu_stop()  local
267 		set_er(0, XTENSA_PMU_PMCTRL(idx));  in xtensa_pmu_stop()
268 		set_er(get_er(XTENSA_PMU_PMSTAT(idx)),  in xtensa_pmu_stop()
269 		       XTENSA_PMU_PMSTAT(idx));  in xtensa_pmu_stop()
275 		xtensa_perf_event_update(event, &event->hw, idx);  in xtensa_pmu_stop()
288 	int idx = hwc->idx;  in xtensa_pmu_add()  local
290 	if (__test_and_set_bit(idx, ev->used_mask)) {  in xtensa_pmu_add()
291 		idx = find_first_zero_bit(ev->used_mask,  in xtensa_pmu_add()
293 		if (idx == XCHAL_NUM_PERF_COUNTERS)  in xtensa_pmu_add()
296 		__set_bit(idx, ev->used_mask);  in xtensa_pmu_add()
297 		hwc->idx = idx;  in xtensa_pmu_add()
299 	ev->event[idx] = event;  in xtensa_pmu_add()
315 	__clear_bit(event->hw.idx, ev->used_mask);  in xtensa_pmu_del()
321 	xtensa_perf_event_update(event, &event->hw, event->hw.idx);  in xtensa_pmu_read()