149 	struct arm_ccn_dt, pmu), struct arm_ccn, dt)
189 	struct arm_ccn_dt dt;  member
460 		return &ccn->dt.cmp_mask[i].l;  in arm_ccn_pmu_get_cmp_mask()
462 		return &ccn->dt.cmp_mask[i].h;  in arm_ccn_pmu_get_cmp_mask()
550 	return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu);  in arm_ccn_pmu_cpumask_show()
646 				ccn->dt.pmu_counters_mask))  in arm_ccn_pmu_event_alloc()
650 		ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;  in arm_ccn_pmu_event_alloc()
656 	hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,  in arm_ccn_pmu_event_alloc()
667 	ccn->dt.pmu_counters[hw->idx].source = source;  in arm_ccn_pmu_event_alloc()
679 		clear_bit(hw->idx, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_alloc()
684 	ccn->dt.pmu_counters[hw->idx].event = event;  in arm_ccn_pmu_event_alloc()
695 		clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_release()
698 				ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_event_release()
706 		clear_bit(hw->idx, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_release()
709 	ccn->dt.pmu_counters[hw->idx].source = NULL;  in arm_ccn_pmu_event_release()
710 	ccn->dt.pmu_counters[hw->idx].event = NULL;  in arm_ccn_pmu_event_release()
752 	event->cpu = cpumask_first(&ccn->dt.cpu);  in arm_ccn_pmu_event_init()
846 		res = readq(ccn->dt.base + CCN_DT_PMCCNTR);  in arm_ccn_pmu_read_counter()
849 		writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);  in arm_ccn_pmu_read_counter()
850 		while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))  in arm_ccn_pmu_read_counter()
852 		writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);  in arm_ccn_pmu_read_counter()
853 		res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;  in arm_ccn_pmu_read_counter()
855 		res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);  in arm_ccn_pmu_read_counter()
858 		res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));  in arm_ccn_pmu_read_counter()
898 	spin_lock(&ccn->dt.config_lock);  in arm_ccn_pmu_xp_dt_config()
906 	spin_unlock(&ccn->dt.config_lock);  in arm_ccn_pmu_xp_dt_config()
924 		hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),  in arm_ccn_pmu_event_start()
941 		hrtimer_cancel(&ccn->dt.hrtimer);  in arm_ccn_pmu_event_stop()
961 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_xp_watchpoint_config()
966 	u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;  in arm_ccn_pmu_xp_watchpoint_config()
967 	u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;  in arm_ccn_pmu_xp_watchpoint_config()
1009 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_xp_event_config()
1030 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_node_event_config()
1077 	spin_lock(&ccn->dt.config_lock);  in arm_ccn_pmu_event_config()
1081 	val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);  in arm_ccn_pmu_event_config()
1085 	writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);  in arm_ccn_pmu_event_config()
1097 	spin_unlock(&ccn->dt.config_lock);  in arm_ccn_pmu_event_config()
1131 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)  in arm_ccn_pmu_overflow_handler()  argument
1133 	u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);  in arm_ccn_pmu_overflow_handler()
1139 	writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);  in arm_ccn_pmu_overflow_handler()
1144 		struct perf_event *event = dt->pmu_counters[idx].event;  in arm_ccn_pmu_overflow_handler()
1161 	struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,  in arm_ccn_pmu_timer_handler()  local
1166 	arm_ccn_pmu_overflow_handler(dt);  in arm_ccn_pmu_timer_handler()
1177 	struct arm_ccn_dt *dt = container_of(nb, struct arm_ccn_dt, cpu_nb);  in arm_ccn_pmu_cpu_notifier()  local
1178 	struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);  in arm_ccn_pmu_cpu_notifier()
1184 		if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu))  in arm_ccn_pmu_cpu_notifier()
1189 		perf_pmu_migrate_context(&dt->pmu, cpu, target);  in arm_ccn_pmu_cpu_notifier()
1190 		cpumask_set_cpu(target, &dt->cpu);  in arm_ccn_pmu_cpu_notifier()
1192 			WARN_ON(irq_set_affinity(ccn->irq, &dt->cpu) != 0);  in arm_ccn_pmu_cpu_notifier()
1210 	ccn->dt.base = ccn->base + CCN_REGION_SIZE;  in arm_ccn_pmu_init()
1211 	spin_lock_init(&ccn->dt.config_lock);  in arm_ccn_pmu_init()
1212 	writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);  in arm_ccn_pmu_init()
1213 	writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);  in arm_ccn_pmu_init()
1215 			ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_init()
1216 	writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);  in arm_ccn_pmu_init()
1226 	ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;  in arm_ccn_pmu_init()
1227 	ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;  in arm_ccn_pmu_init()
1228 	ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;  in arm_ccn_pmu_init()
1229 	ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;  in arm_ccn_pmu_init()
1230 	ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;  in arm_ccn_pmu_init()
1231 	ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);  in arm_ccn_pmu_init()
1232 	ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;  in arm_ccn_pmu_init()
1233 	ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);  in arm_ccn_pmu_init()
1236 	ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);  in arm_ccn_pmu_init()
1237 	if (ccn->dt.id == 0) {  in arm_ccn_pmu_init()
1240 		int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);  in arm_ccn_pmu_init()
1243 		snprintf(name, len + 1, "ccn_%d", ccn->dt.id);  in arm_ccn_pmu_init()
1247 	ccn->dt.pmu = (struct pmu) {  in arm_ccn_pmu_init()
1261 		hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,  in arm_ccn_pmu_init()
1263 		ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;  in arm_ccn_pmu_init()
1267 	cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu);  in arm_ccn_pmu_init()
1273 	ccn->dt.cpu_nb.notifier_call = arm_ccn_pmu_cpu_notifier;  in arm_ccn_pmu_init()
1274 	ccn->dt.cpu_nb.priority = CPU_PRI_PERF + 1,  in arm_ccn_pmu_init()
1275 	err = register_cpu_notifier(&ccn->dt.cpu_nb);  in arm_ccn_pmu_init()
1281 		err = irq_set_affinity(ccn->irq, &ccn->dt.cpu);  in arm_ccn_pmu_init()
1288 	err = perf_pmu_register(&ccn->dt.pmu, name, -1);  in arm_ccn_pmu_init()
1296 	unregister_cpu_notifier(&ccn->dt.cpu_nb);  in arm_ccn_pmu_init()
1298 	ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);  in arm_ccn_pmu_init()
1301 	writel(0, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_init()
1310 	unregister_cpu_notifier(&ccn->dt.cpu_nb);  in arm_ccn_pmu_cleanup()
1313 	writel(0, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_cleanup()
1314 	perf_pmu_unregister(&ccn->dt.pmu);  in arm_ccn_pmu_cleanup()
1315 	ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);  in arm_ccn_pmu_cleanup()
1422 		res = arm_ccn_pmu_overflow_handler(&ccn->dt);  in arm_ccn_irq_handler()