65 	u8 __iomem *registers;  member
185 	intel_private.registers = ioremap(reg_addr, KB(64));  in i810_setup()
186 	if (!intel_private.registers)  in i810_setup()
190 	       intel_private.registers+I810_PGETBL_CTL);  in i810_setup()
194 	if ((readl(intel_private.registers+I810_DRAM_CTL)  in i810_setup()
206 	writel(0, intel_private.registers+I810_PGETBL_CTL);  in i810_cleanup()
370 			rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);  in intel_gtt_stolen_size()
443 	pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);  in i965_adjust_pgetbl_size()
445 	writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);  in i965_adjust_pgetbl_size()
448 	pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);  in i965_adjust_pgetbl_size()
451 	writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);  in i965_adjust_pgetbl_size()
479 	pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);  in i965_gtt_total_entries()
568 	iounmap(intel_private.registers);  in intel_gtt_cleanup()
621 		readl(intel_private.registers+I810_PGETBL_CTL)  in intel_gtt_init()
643 		iounmap(intel_private.registers);  in intel_gtt_init()
719 	writel(readl(intel_private.registers+I830_HIC) | (1<<31),  in i830_chipset_flush()
720 	       intel_private.registers+I830_HIC);  in i830_chipset_flush()
722 	while (readl(intel_private.registers+I830_HIC) & (1<<31)) {  in i830_chipset_flush()
768 		writel(0, intel_private.registers+GFX_FLSH_CNTL);  in intel_enable_gtt()
770 	reg = intel_private.registers+I810_PGETBL_CTL;  in intel_enable_gtt()
780 		writel(0, intel_private.registers+GFX_FLSH_CNTL);  in intel_enable_gtt()
792 	intel_private.registers = ioremap(reg_addr, KB(64));  in i830_setup()
793 	if (!intel_private.registers)  in i830_setup()
1119 	intel_private.registers = ioremap(reg_addr, size);  in i9xx_setup()
1120 	if (!intel_private.registers)  in i9xx_setup()