164 					  ep->registers + fpga_msg_ctrl_reg);  in xillybus_isr()
299 	iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */  in xillybus_isr()
379 			  ep->registers + fpga_dma_bufaddr_lowaddr_reg);  in xilly_get_dma_buffers()
381 			  ep->registers + fpga_dma_bufaddr_highaddr_reg);  in xilly_get_dma_buffers()
389 				  ep->registers + fpga_dma_bufno_reg);  in xilly_get_dma_buffers()
396 				  ep->registers + fpga_dma_bufno_reg);  in xilly_get_dma_buffers()
620 		  endpoint->registers + fpga_buf_ctrl_reg);  in xilly_obtain_idt()
782 					  channel->endpoint->registers +  in xillybus_read()
867 					  channel->endpoint->registers +  in xillybus_read()
873 					  channel->endpoint->registers +  in xillybus_read()
962 				  channel->endpoint->registers +  in xillybus_read()
1079 			  channel->endpoint->registers + fpga_buf_offset_reg);  in xillybus_myflush()
1084 			  channel->endpoint->registers + fpga_buf_ctrl_reg);  in xillybus_myflush()
1321 					  channel->endpoint->registers +  in xillybus_write()
1327 					  channel->endpoint->registers +  in xillybus_write()
1521 				  channel->endpoint->registers +  in xillybus_open()
1542 				  channel->endpoint->registers +  in xillybus_open()
1586 				  channel->endpoint->registers +  in xillybus_release()
1600 				  channel->endpoint->registers +  in xillybus_release()
1706 		  channel->endpoint->registers + fpga_buf_offset_reg);  in xillybus_llseek()
1710 		  channel->endpoint->registers + fpga_buf_ctrl_reg);  in xillybus_llseek()
1924 		  endpoint->registers + fpga_dma_control_reg);  in xilly_quiesce()
1963 	iowrite32(1, endpoint->registers + fpga_endian_reg);  in xillybus_endpoint_discovery()
1978 	iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg);  in xillybus_endpoint_discovery()
1987 		  endpoint->registers + fpga_dma_control_reg);  in xillybus_endpoint_discovery()
1999 		  endpoint->registers + fpga_dma_control_reg);  in xillybus_endpoint_discovery()