48 	struct iproc_asiu_clk *clk = to_asiu_clk(hw);  in iproc_asiu_clk_enable()  local
49 	struct iproc_asiu *asiu = clk->asiu;  in iproc_asiu_clk_enable()
53 	if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)  in iproc_asiu_clk_enable()
56 	val = readl(asiu->gate_base + clk->gate.offset);  in iproc_asiu_clk_enable()
57 	val |= (1 << clk->gate.en_shift);  in iproc_asiu_clk_enable()
58 	writel(val, asiu->gate_base + clk->gate.offset);  in iproc_asiu_clk_enable()
65 	struct iproc_asiu_clk *clk = to_asiu_clk(hw);  in iproc_asiu_clk_disable()  local
66 	struct iproc_asiu *asiu = clk->asiu;  in iproc_asiu_clk_disable()
70 	if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)  in iproc_asiu_clk_disable()
73 	val = readl(asiu->gate_base + clk->gate.offset);  in iproc_asiu_clk_disable()
74 	val &= ~(1 << clk->gate.en_shift);  in iproc_asiu_clk_disable()
75 	writel(val, asiu->gate_base + clk->gate.offset);  in iproc_asiu_clk_disable()
81 	struct iproc_asiu_clk *clk = to_asiu_clk(hw);  in iproc_asiu_clk_recalc_rate()  local
82 	struct iproc_asiu *asiu = clk->asiu;  in iproc_asiu_clk_recalc_rate()
87 		clk->rate = 0;  in iproc_asiu_clk_recalc_rate()
92 	val = readl(asiu->div_base + clk->div.offset);  in iproc_asiu_clk_recalc_rate()
93 	if ((val & (1 << clk->div.en_shift)) == 0) {  in iproc_asiu_clk_recalc_rate()
94 		clk->rate = parent_rate;  in iproc_asiu_clk_recalc_rate()
99 	div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);  in iproc_asiu_clk_recalc_rate()
101 	div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);  in iproc_asiu_clk_recalc_rate()
104 	clk->rate = parent_rate / (div_h + div_l);  in iproc_asiu_clk_recalc_rate()
106 		 __func__, clk->rate, parent_rate, div_h, div_l);  in iproc_asiu_clk_recalc_rate()
108 	return clk->rate;  in iproc_asiu_clk_recalc_rate()
132 	struct iproc_asiu_clk *clk = to_asiu_clk(hw);  in iproc_asiu_clk_set_rate()  local
133 	struct iproc_asiu *asiu = clk->asiu;  in iproc_asiu_clk_set_rate()
142 		val = readl(asiu->div_base + clk->div.offset);  in iproc_asiu_clk_set_rate()
143 		val &= ~(1 << clk->div.en_shift);  in iproc_asiu_clk_set_rate()
144 		writel(val, asiu->div_base + clk->div.offset);  in iproc_asiu_clk_set_rate()
156 	val = readl(asiu->div_base + clk->div.offset);  in iproc_asiu_clk_set_rate()
157 	val |= 1 << clk->div.en_shift;  in iproc_asiu_clk_set_rate()
159 		val &= ~(bit_mask(clk->div.high_width)  in iproc_asiu_clk_set_rate()
160 			 << clk->div.high_shift);  in iproc_asiu_clk_set_rate()
161 		val |= div_h << clk->div.high_shift;  in iproc_asiu_clk_set_rate()
163 		val &= ~(bit_mask(clk->div.high_width)  in iproc_asiu_clk_set_rate()
164 			 << clk->div.high_shift);  in iproc_asiu_clk_set_rate()
167 		val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);  in iproc_asiu_clk_set_rate()
168 		val |= div_l << clk->div.low_shift;  in iproc_asiu_clk_set_rate()
170 		val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);  in iproc_asiu_clk_set_rate()
172 	writel(val, asiu->div_base + clk->div.offset);  in iproc_asiu_clk_set_rate()
220 		struct clk *clk;  in iproc_asiu_setup()  local
243 		clk = clk_register(NULL, &asiu_clk->hw);  in iproc_asiu_setup()
244 		if (WARN_ON(IS_ERR(clk)))  in iproc_asiu_setup()
246 		asiu->clk_data.clks[i] = clk;  in iproc_asiu_setup()