27 #define CDCE706_PLL_M_LOW(pll)		(1 + 3 * (pll))  argument
28 #define CDCE706_PLL_N_LOW(pll)		(2 + 3 * (pll))  argument
29 #define CDCE706_PLL_HI(pll)		(3 + 3 * (pll))  argument
40 #define CDCE706_PLL_MUX_MASK(pll)	(0x80 >> (pll))  argument
48 #define CDCE706_PLL_FVCO_MASK(pll)	(0x80 >> (pll))  argument
89 	struct cdce706_hw_data pll[3];  member
530 	for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) {  in cdce706_register_plls()
542 		cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8);  in cdce706_register_plls()
543 		cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) <<  in cdce706_register_plls()
545 		cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i);  in cdce706_register_plls()
548 			cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux);  in cdce706_register_plls()
551 	ret = cdce706_register_hw(cdce, cdce->pll,  in cdce706_register_plls()
552 				  ARRAY_SIZE(cdce->pll),  in cdce706_register_plls()