63 	struct clk_cdce925_pll pll[NUMBER_OF_PLLS];  member
205 	u8 pll[4]; /* Bits are spread out over 4 byte registers */  in cdce925_pll_prepare()  local
233 		pll[0] = n >> 4;  in cdce925_pll_prepare()
234 		pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);  in cdce925_pll_prepare()
235 		pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);  in cdce925_pll_prepare()
236 		pll[3] = ((q & 0x07) << 5) | (p << 2) |  in cdce925_pll_prepare()
239 		for (i = 0; i < ARRAY_SIZE(pll); ++i)  in cdce925_pll_prepare()
241 				reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);  in cdce925_pll_prepare()
357 	struct clk *pll = clk_get_parent(hw->clk);  in cdce925_clk_best_parent_rate()  local
358 	struct clk *root = clk_get_parent(pll);  in cdce925_clk_best_parent_rate()
378 		long pll_rate = clk_round_rate(pll, target_rate);  in cdce925_clk_best_parent_rate()
622 		data->pll[i].chip = data;  in cdce925_probe()
623 		data->pll[i].hw.init = &init;  in cdce925_probe()
624 		data->pll[i].index = i;  in cdce925_probe()
625 		clk = devm_clk_register(&client->dev, &data->pll[i].hw);  in cdce925_probe()