Lines Matching refs:CLKSEL_VALID
46 #define CLKSEL_VALID 1 macro
122 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
123 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
124 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
130 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
131 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
132 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
138 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
139 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
140 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
146 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
147 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
148 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
154 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
155 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
156 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
157 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
163 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
164 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
165 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
166 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
172 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
173 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
174 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
175 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
176 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
182 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
183 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
184 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
185 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
186 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
192 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
193 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
199 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
200 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
201 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
202 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
209 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
213 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
217 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
225 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
229 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
237 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
241 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
255 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
256 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
263 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
272 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
273 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
274 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
280 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
288 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
289 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
290 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
291 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
292 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
293 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
300 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
301 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
302 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
303 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
304 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
305 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
306 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
312 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
313 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
314 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
315 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
316 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
318 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
319 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
325 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
326 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
327 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
328 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
329 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
335 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
336 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
337 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
338 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
339 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
340 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
690 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()