Lines Matching refs:PLATFORM_PLL
29 #define PLATFORM_PLL 0 macro
291 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
304 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
312 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
328 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
338 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
357 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
369 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
374 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
389 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
404 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
409 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
419 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; in t1040_init_periph()
790 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); in create_one_cmux()
952 case PLATFORM_PLL: in create_one_pll()
972 if (idx == PLATFORM_PLL) in create_one_pll()
988 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) in create_one_pll()
1071 legacy_pll_init(np, PLATFORM_PLL); in pltfrm_pll_init()
1132 pll = &cg->pll[PLATFORM_PLL]; in clockgen_clk_get()