Lines Matching refs:PLL_DIV2
25 #define PLL_DIV2 1 macro
123 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
132 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
139 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
148 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
155 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
157 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
164 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
166 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
173 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
175 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
184 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
186 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
193 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
200 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
202 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
255 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
273 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
280 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
288 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
292 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
301 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
305 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
312 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
314 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
318 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
325 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
329 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
335 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
339 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
355 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
357 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
367 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
369 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
372 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
374 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
380 int div = PLL_DIV2; in p5020_init_periph()
389 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
395 int div = PLL_DIV2; in p5040_init_periph()
404 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
409 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()