Lines Matching refs:cg
80 void (*init_periph)(struct clockgen *cg);
100 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) in cg_out() argument
102 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
108 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) in cg_in() argument
112 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
348 static void __init p2041_init_periph(struct clockgen *cg) in p2041_init_periph() argument
352 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
355 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
357 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
360 static void __init p4080_init_periph(struct clockgen *cg) in p4080_init_periph() argument
364 reg = ioread32be(&cg->guts->rcwsr[7]); in p4080_init_periph()
367 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
369 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
372 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
374 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
377 static void __init p5020_init_periph(struct clockgen *cg) in p5020_init_periph() argument
382 reg = ioread32be(&cg->guts->rcwsr[7]); in p5020_init_periph()
387 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
389 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
392 static void __init p5040_init_periph(struct clockgen *cg) in p5040_init_periph() argument
397 reg = ioread32be(&cg->guts->rcwsr[7]); in p5040_init_periph()
402 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
404 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
407 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
409 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
412 static void __init t1023_init_periph(struct clockgen *cg) in t1023_init_periph() argument
414 cg->fman[0] = cg->hwaccel[1]; in t1023_init_periph()
417 static void __init t1040_init_periph(struct clockgen *cg) in t1040_init_periph() argument
419 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; in t1040_init_periph()
422 static void __init t2080_init_periph(struct clockgen *cg) in t2080_init_periph() argument
424 cg->fman[0] = cg->hwaccel[0]; in t2080_init_periph()
427 static void __init t4240_init_periph(struct clockgen *cg) in t4240_init_periph() argument
429 cg->fman[0] = cg->hwaccel[3]; in t4240_init_periph()
430 cg->fman[1] = cg->hwaccel[4]; in t4240_init_periph()
628 struct clockgen *cg; member
649 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
660 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
684 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg, in get_pll_div() argument
696 return &cg->pll[pll].div[div]; in get_pll_div()
699 static struct clk * __init create_mux_common(struct clockgen *cg, in create_mux_common() argument
720 div = get_pll_div(cg, hwc, i); in create_mux_common()
744 hwc->cg = cg; in create_mux_common()
757 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) in create_one_cmux() argument
769 hwc->reg = cg->regs + 0x20 * idx; in create_one_cmux()
770 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; in create_one_cmux()
779 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in create_one_cmux()
780 div = get_pll_div(cg, hwc, clksel); in create_one_cmux()
790 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); in create_one_cmux()
792 if (cg->info.flags & CG_CMUX_GE_PLAT) in create_one_cmux()
797 return create_mux_common(cg, hwc, &cmux_ops, min_rate, in create_one_cmux()
801 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) in create_one_hwaccel() argument
809 hwc->reg = cg->regs + 0x20 * idx + 0x10; in create_one_hwaccel()
810 hwc->info = cg->info.hwaccel[idx]; in create_one_hwaccel()
812 return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0, in create_one_hwaccel()
816 static void __init create_muxes(struct clockgen *cg) in create_muxes() argument
820 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { in create_muxes()
821 if (cg->info.cmux_to_group[i] < 0) in create_muxes()
823 if (cg->info.cmux_to_group[i] >= in create_muxes()
824 ARRAY_SIZE(cg->info.cmux_groups)) { in create_muxes()
829 cg->cmux[i] = create_one_cmux(cg, i); in create_muxes()
832 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { in create_muxes()
833 if (!cg->info.hwaccel[i]) in create_muxes()
836 cg->hwaccel[i] = create_one_hwaccel(cg, i); in create_muxes()
940 static void __init create_one_pll(struct clockgen *cg, int idx) in create_one_pll() argument
944 struct clockgen_pll *pll = &cg->pll[idx]; in create_one_pll()
947 if (!(cg->info.pll_mask & (1 << idx))) in create_one_pll()
950 if (cg->info.flags & CG_VER3) { in create_one_pll()
953 reg = cg->regs + 0x60080; in create_one_pll()
956 reg = cg->regs + 0x80; in create_one_pll()
959 reg = cg->regs + 0xa0; in create_one_pll()
962 reg = cg->regs + 0x10080; in create_one_pll()
965 reg = cg->regs + 0x100a0; in create_one_pll()
973 reg = cg->regs + 0xc00; in create_one_pll()
975 reg = cg->regs + 0x800 + 0x20 * (idx - 1); in create_one_pll()
979 mult = cg_in(cg, reg); in create_one_pll()
987 if ((cg->info.flags & CG_VER3) || in create_one_pll()
988 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) in create_one_pll()
1011 static void __init create_plls(struct clockgen *cg) in create_plls() argument
1015 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) in create_plls()
1016 create_one_pll(cg, i); in create_plls()
1097 struct clockgen *cg = data; in clockgen_clk_get() local
1114 clk = cg->sysclk; in clockgen_clk_get()
1117 if (idx >= ARRAY_SIZE(cg->cmux)) in clockgen_clk_get()
1119 clk = cg->cmux[idx]; in clockgen_clk_get()
1122 if (idx >= ARRAY_SIZE(cg->hwaccel)) in clockgen_clk_get()
1124 clk = cg->hwaccel[idx]; in clockgen_clk_get()
1127 if (idx >= ARRAY_SIZE(cg->fman)) in clockgen_clk_get()
1129 clk = cg->fman[idx]; in clockgen_clk_get()
1132 pll = &cg->pll[PLATFORM_PLL]; in clockgen_clk_get()