640 static int mux_set_parent(struct clk_hw *hw, u8 idx)  in mux_set_parent()  argument
645 	if (idx >= hwc->num_parents)  in mux_set_parent()
648 	clksel = hwc->parent_to_clksel[idx];  in mux_set_parent()
686 						  int idx)  in get_pll_div()  argument
690 	if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))  in get_pll_div()
693 	pll = hwc->info->clksel[idx].pll;  in get_pll_div()
694 	div = hwc->info->clksel[idx].div;  in get_pll_div()
704 					     const char *fmt, int idx)  in create_mux_common()  argument
713 	snprintf(name, sizeof(name), fmt, idx);  in create_mux_common()
757 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)  in create_one_cmux()  argument
769 	hwc->reg = cg->regs + 0x20 * idx;  in create_one_cmux()
770 	hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];  in create_one_cmux()
798 				 pct80_rate, "cg-cmux%d", idx);  in create_one_cmux()
801 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)  in create_one_hwaccel()  argument
809 	hwc->reg = cg->regs + 0x20 * idx + 0x10;  in create_one_hwaccel()
810 	hwc->info = cg->info.hwaccel[idx];  in create_one_hwaccel()
813 				 "cg-hwaccel%d", idx);  in create_one_hwaccel()
854 	int idx, rc;  in core_mux_init()  local
861 	idx = (res.start & 0xf0) >> 5;  in core_mux_init()
862 	clk = clockgen.cmux[idx];  in core_mux_init()
940 static void __init create_one_pll(struct clockgen *cg, int idx)  in create_one_pll()  argument
944 	struct clockgen_pll *pll = &cg->pll[idx];  in create_one_pll()
947 	if (!(cg->info.pll_mask & (1 << idx)))  in create_one_pll()
951 		switch (idx) {  in create_one_pll()
968 			WARN_ONCE(1, "index %d\n", idx);  in create_one_pll()
972 		if (idx == PLATFORM_PLL)  in create_one_pll()
975 			reg = cg->regs + 0x800 + 0x20 * (idx - 1);  in create_one_pll()
988 	    ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))  in create_one_pll()
997 			 "cg-pll%d-div%d", idx, i + 1);  in create_one_pll()
1019 static void __init legacy_pll_init(struct device_node *np, int idx)  in legacy_pll_init()  argument
1028 	pll = &clockgen.pll[idx];  in legacy_pll_init()
1078 	int idx;  in core_pll_init()  local
1090 		idx = (res.start & 0xf0) >> 5;  in core_pll_init()
1091 		legacy_pll_init(np, CGA_PLL1 + idx);  in core_pll_init()
1100 	u32 type, idx;  in clockgen_clk_get()  local
1108 	idx = clkspec->args[1];  in clockgen_clk_get()
1112 		if (idx != 0)  in clockgen_clk_get()
1117 		if (idx >= ARRAY_SIZE(cg->cmux))  in clockgen_clk_get()
1119 		clk = cg->cmux[idx];  in clockgen_clk_get()
1122 		if (idx >= ARRAY_SIZE(cg->hwaccel))  in clockgen_clk_get()
1124 		clk = cg->hwaccel[idx];  in clockgen_clk_get()
1127 		if (idx >= ARRAY_SIZE(cg->fman))  in clockgen_clk_get()
1129 		clk = cg->fman[idx];  in clockgen_clk_get()
1133 		if (idx >= ARRAY_SIZE(pll->div))  in clockgen_clk_get()
1135 		clk = pll->div[idx].clk;  in clockgen_clk_get()
1146 	pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);  in clockgen_clk_get()