51 	int pll;	/* CGx_PLLn */  member
91 	struct clockgen_pll pll[6];  member
355 		cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;  in p2041_init_periph()
357 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p2041_init_periph()
367 		cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;  in p4080_init_periph()
369 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
372 		cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;  in p4080_init_periph()
374 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
387 		cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;  in p5020_init_periph()
389 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5020_init_periph()
402 		cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;  in p5040_init_periph()
404 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
407 		cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;  in p5040_init_periph()
409 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
419 	cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;  in t1040_init_periph()
688 	int pll, div;  in get_pll_div()  local
693 	pll = hwc->info->clksel[idx].pll;  in get_pll_div()
696 	return &cg->pll[pll].div[div];  in get_pll_div()
790 	plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);  in create_one_cmux()
944 	struct clockgen_pll *pll = &cg->pll[idx];  in create_one_pll()  local
993 	for (i = 0; i < ARRAY_SIZE(pll->div); i++) {  in create_one_pll()
996 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),  in create_one_pll()
1000 				pll->div[i].name, "cg-sysclk", 0, mult, i + 1);  in create_one_pll()
1003 			       __func__, pll->div[i].name, PTR_ERR(clk));  in create_one_pll()
1007 		pll->div[i].clk = clk;  in create_one_pll()
1015 	for (i = 0; i < ARRAY_SIZE(cg->pll); i++)  in create_plls()
1021 	struct clockgen_pll *pll;  in legacy_pll_init()  local
1028 	pll = &clockgen.pll[idx];  in legacy_pll_init()
1031 	BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);  in legacy_pll_init()
1041 		subclks[0] = pll->div[0].clk;  in legacy_pll_init()
1042 		subclks[1] = pll->div[1].clk;  in legacy_pll_init()
1043 		subclks[2] = pll->div[3].clk;  in legacy_pll_init()
1045 		subclks[0] = pll->div[0].clk;  in legacy_pll_init()
1046 		subclks[1] = pll->div[1].clk;  in legacy_pll_init()
1047 		subclks[2] = pll->div[2].clk;  in legacy_pll_init()
1048 		subclks[3] = pll->div[3].clk;  in legacy_pll_init()
1099 	struct clockgen_pll *pll;  in clockgen_clk_get()  local
1132 		pll = &cg->pll[PLATFORM_PLL];  in clockgen_clk_get()
1133 		if (idx >= ARRAY_SIZE(pll->div))  in clockgen_clk_get()
1135 		clk = pll->div[idx].clk;  in clockgen_clk_get()