Lines Matching refs:divby4
649 int divby4; in si5351_msynth_round_rate() local
661 divby4 = 0; in si5351_msynth_round_rate()
663 divby4 = 1; in si5351_msynth_round_rate()
671 if (divby4 == 0) { in si5351_msynth_round_rate()
696 if (divby4) { in si5351_msynth_round_rate()
698 divby4 = 0; in si5351_msynth_round_rate()
730 if (divby4) { in si5351_msynth_round_rate()
748 __func__, clk_hw_get_name(hw), a, b, c, divby4, in si5351_msynth_round_rate()
760 int divby4 = 0; in si5351_msynth_set_rate() local
766 divby4 = 1; in si5351_msynth_set_rate()
772 (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0); in si5351_msynth_set_rate()
782 divby4, parent_rate, rate); in si5351_msynth_set_rate()